Zilog Z80230 Uživatelský manuál Strana 271
- Strana / 394
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
SCC/ESCC
User Manual
UM010903-0515 Application Notes
264
can be interconnected for communication between on-board serial controllers, or they can be con-
nected to the user’s custom communications hardware on another board. As a third option, they
can be connected to three on-board serial interfaces via the connector blocks labelled J13 through
J15.
Two of the on-board serial interfaces use EIA-RS-232 signal levels and pin arrangement. 25-pin D
connectors J1A or J2A are configured as DTE, while J1B and J2B are configured as DCE. These
serial interfaces are used by connecting one of the J5-J10 to J13 or J14, respectively. J1B is typi-
cally used for connection to the user’s PC or terminal.
The third on-board serial interface uses EIA-422 signal levels on connector J3A, J3B, or J4 and is
used by connecting one of J5-J10 to J15. The 25-pin D connector J3A uses the DTE pin arrange-
ment put forth in the EIA-530 standard. J3B is a DCE version of EIA-530, while the 8-pin circular
DIN connector, J4, is compatible with the Apple Macintosh Plus and later Macintoshes, and thus
with AppleTalk/LocalTalk equipment.
Table and Table summarize the serial interface connectors
.
The pin-out of the J5-J10 connectors is consistent, but may not be identical because of differences
among the various serial controllers. These differences are listed in Table .
Controller Port Connectors
Serial Controller Channel w/on/off Board Hardware Connect to this (these) Connector Blocks
(E)SCC Channel A J5
(E)SCC Channel B J6
ISCC Channel A J7
ISCC Channel B J8
IUSC J9 (J11 for Port pins)
(M)USC J10 (J12 for MUSC Port pins or USC
Channel B
On-Board Line Driver/Receiver Connectors
Using a Serial Chip Controller w/following on-chip Serial
Interface Connect Connectors in Table 6 to:
J1A or J1B EIA-RS-232 Console J13
J2A or J2B EIA-RS-232 J14
RS-422 Differential: J3A or J3B EIA-530 or J4 Circular-8 (DIN) J15
- SCC/ESCC 1
- UM010903-0515 2
- Revision History 3
- Table of Contents 4
- SCC’s Capabilities 9
- User Manual 13
- SCC Block Diagram 13
- Pin Descriptions 14
- Z85X30 DIP Pin Assignments 17
- Z85X30 PLCC Pin Assignments 18
- Z80X30 DIP Pin Assignments 19
- Interfacing the SCC/ESCC 24
- Z80X30 Write Cycle Timing 25
- Z80X30 Register Access 28
- Z80C30 Register Enhancement 31
- Z80230 Register Enhancements 32
- Z80X30 Reset 33
- Z85X30 Interface Timing 34
- Z85X30 Read Cycle Timing 35
- Z85X30 Write Cycle Timing 35
- D7-D0 Vector 36
- Z85X30 Register Access 37
- Z85C30 Register Enhancement 39
- Z85X30 Reset 41
- Interface Programming 42
- I/O Programming Introduction 43
- Interrupts 43
- External/Status Channel A 44
- Receive Channel B 44
- Transmit Channel B 44
- * Always 0 In B Channel 47
- Daisy-Chain Resolution 48
- Interrupt Acknowledge 51
- The Receiver Interrupt 52
- Receive Interrupts Disabled 53
- Conditio 56
- External/Status Interrupts 63
- Break/Abort 65
- Transmit Underrun/EOM 65
- CTS/DCD 66
- Zero Count 66
- Sync/Hunt 66
- Block/DMA Transfer 67
- SYNC Modes 68
- ASYNC Modes 68
- Wait On Receive 69
- DMA Requests 70
- DMA Request On Receive 74
- AD7-AD0 Receive DataWR8 75
- Test Functions 76
- Introduction 78
- Baud Rate Generator 78
- Data Encoding/Decoding 81
- Clock Selection 90
- Clock Multiplexer 92
- BRG Clock Source = /RTXC 93
- Crystal Oscillator 94
- Data Communication Modes 95
- Transmit Data Path 96
- Asynchronous Mode 99
- Asynchronous Transmit 100
- Asynchronous Receive 103
- Asynchronous Initialization 105
- Reg Bit No Description 107
- WR4 3 (=0) select sync mode 107
- State Changes in One 113
- /RTxC Clock Cycle 113
- SDLC Transmit 121
- SDLC Receive 127
- SDLC Frame Status FIFO 133
- Frame Status FIFO Circuitr 135
- Interface 135
- SDLC Loop Mode 137
- SDLC Loop Mode Receive 140
- SDLC Loop Mode Transmit 140
- Register Descriptions 143
- Write Registers 145
- Definition) 149
- Z85X30 Register Map 151
- Time Constant 175
- Clock Frequency 175
- Read Registers 181
- Read Register 1 185
- Read Register 2 187
- Read Register 3 188
- Read Register 8 191
- Read Register 10 192
- Read Register 12 193
- Read Register 13 194
- Read Register 15 194
- Application Notes 195
- Abstract 217
- Features 217
- Discussion 217
- Interfaces 218
- Z180 to Memory Interface 218
- EPROM Interface 220
- SRAM Interface 222
- SRAM Read Cycle 222
- SRAM Write Cycle 223
- Memory Interface Logic 223
- Physical Memory Address Map 225
- Z180 to I/O Interface 226
- Z180 I/O Write Cycle Timing 227
- Z180 to SCC Interface 230
- CPU Hardware Interfacing 230
- Data Bus Signals 230
- System Control Signals 230
- Interrupt Control 231
- SCC I/O Operation 231
- Read Cycle Timing 231
- Write Cycle Timing 232
- SCC Interrupt Operation 232
- Input/Output Cycles 234
- Z180 MPU to SCC Interface 234
- SCC I/O Read/Write Cycle 235
- I/O Read Cycle 235
- I/O Write Cycle 235
- Using EPLD 242
- System Checkout 243
- Software Considerations 244
- SCC Read Cycle Proof 244
- SCC Write Cycle Proof 244
- Interrupt Acknowledge Cycle 244
- (Continued) 246
- Summary 256
- General Description 257
- Processor 258
- Address Map 260
- (PBA)+511 269
- Serial Interfacing 270
- DMA channel 272
- Jumper Summary 276
- Control EPLD for 186 Board 278
- SCC EPLD for 186 Board 279
- DMA EPLD for 186 Board 280
- NMI Field for 186 Board 281
- Operation 295
- ESCC Controller 318
- Questions and Answers 382
- Customer Support 394
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