Zilog Z80230 Uživatelský manuál

Copyright © 2015 by Zilog®, Inc. All rights reserved.www.zilog.comUM010903-0515User Manual SCC/ESCC

SCC/ESCCUser ManualUM010903-0515 General Description3– Automatic Cyclic Redundancy Check (CRC) generation/detection •SDLC/HDLC capabilities: – Abort s

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes93The SCC supports Asynchronous mode with a number of programmable options including the numb

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes94 An additional bit, carrying parity information, may be automatically appended to every tra

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes95The SCC may be programmed to accept a transmit clock that is one, sixteen, thirty-two, or s

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes96D2 also is affected by the state of WR7' bit D5. The All Sent bit, bit D0 of RR1, can

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes97The SCC may be programmed to accept a receive clock that is one, sixteen, thirty-two, or si

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes98the state of WR7' D3. The RCA bit is set if there is at least one byte available, rega

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes99In synchronous communications, the bit cell boundaries are referenced to a clock signal com

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes100Byte-Oriented Synchronous Transmit Once Synchronous mode has been selected, any of three o

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes101In character-oriented modes, a special bit pattern is used to provide character synchroniz

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes102The SCC does not automatically preset the CRC generator in byte Synchronous modes, so this

SCC/ESCCUser ManualUM010903-0515 General Description4– Improved functionality to ease sending back-to back frames – Automatic SDLC opening Flag transm

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes103ing the transmission of the CRC, the 16-bit transmission is completed, but the remaining b

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes104Once the sync character-oriented mode has been selected, any of the four sync character le

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes105assembly begins on the rising edge of the receive clock. This immediately precedes the act

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes106In all cases except External Sync mode, the /SYNC pin is an output that is driven Low by t

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes107The character length can be changed at any time before the new number of bits has been ass

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes108Some synchronous protocols require that certain characters be excluded from CRC calculatio

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes109After eight-bit times, B is loaded into the receive data FIFO. The CRC remains disabled ev

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes110A summary is listed in Table on page 111. Refer to a detailed example of using the SCC in

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes111Transmitter/Receiver Synchronization The SCC contains a transmitter-to-receiver synchroniz

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes112and begins sending sync characters. Beyond this point the receiver and transmitter are aga

SCC/ESCCUser ManualUM010903-0515 General Description5– Receive FIFO automatically unlocked for special receive interrupts when using the SDLC status F

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes113Bit-oriented Synchronous (SDLC/HDLC) Mode Synchronous Data Link Control mode (SDLC) uses s

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes114flag, or an idle. This means that when two frames follow one another, the intervening flag

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes115necessary to reset the WR10 D3 to idle flag, wait 8-bit times, and then write data to the

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes116Only the CRC-CCITT polynomial is used in SDLC mode. This is selected by setting bit D2 in

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes117 The SCC sets the Tx Underrun/EOM latch when the CRC or abort is loaded into the shift reg

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes118Modem Control signals related to SDLC Transmit There are two modem control signals associa

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes119function is enabled in the ESCC to guarantee that the ESCC does not generate the edge befo

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes120port; the CPU needs time to determine whether or not the last bit of the closing flag has

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes121The receiver automatically enters Hunt mode if an abort is received. Because the receiver

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes122An additional bit carrying parity information is selected by setting bit D6 of WR4 to 1. T

SCC/ESCCUser ManualUM010903-0515 General Description6SCC Block DiagramTransmit LogChannelAReceive and Transmit Clock MulTransmit FIFONMOS/CMOS: 1 bESC

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes123Residue Codes As indicated in the table, these bits allow the processor to determine those

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes124the top of the FIFO can cause a special receive condition. The processor then reads RR1 to

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes125In addition to searching the data stream for flags, the receiver in the SCC also watches f

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes126SDLC Frame Status FIFO This feature is not available on the NMOS version. On the CMOS vers

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes127the status FIFO for verification by the CPU. The CRC checker is automatically reset in pre

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes128FIFO Detail. For a better understanding of details of the FIFO operation, refer to the blo

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes129go directly to the bus interface (the FIFO pointer logic is reset either when disabled or

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes130 SDLC Byte Counting Detail SDLC Status FIFO Anti-Lock Feature (ESCC only). When the Frame

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes131The secondary station can place its own message on the loop only at specific times. The co

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes132the CPU writes its data bytes to the SCC, just as in normal SDLC frame transmission. When

SCC/ESCCUser ManualUM010903-0515 General Description7Pin Descriptions The SCC pins are divided into seven functional groups: Address/Data, Bus Timing

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes133SDLC Loop Mode Receive SDLC Loop mode is quite similar to SDLC mode except that two additi

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes134mode, and then WR10 to select the CRC preset value and program the Mark/Flag idle bit. The

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes135processor may either write the first character to the transmit buffer and wait for a trans

SCC/ESCCUser ManualUM010903-0515 Register Descriptions136Register Descriptions Introduction This section describes the functions of the various bits i

SCC/ESCCUser ManualUM010903-0515 Register Descriptions137 WR15 External status interrupt enable control Notes1. ESCC and 85C30 only. 2. On the ESCC an

SCC/ESCCUser ManualUM010903-0515 Register Descriptions138Among these registers, WR9 (Master Interrupt Control and Reset register) can be accessed thro

SCC/ESCCUser ManualUM010903-0515 Register Descriptions139The following sections describe WR registers in detail: Write Register 0 (Command Register) W

SCC/ESCCUser ManualUM010903-0515 Register Descriptions140Underrun selected, the SCC sends an abort and Flag on underrun if the TX Underrun/EOM latch h

SCC/ESCCUser ManualUM010903-0515 Register Descriptions141 Write Register 0 in the Z80X30 At the start of the CRC transmission, the Tx Under-run/EOM la

SCC/ESCCUser ManualUM010903-0515 Register Descriptions142nal/Status Interrupt has not yet been issued) and this condition persists until after the com

SCC/ESCCUser ManualUM010903-0515 General Description8The signal functionality and pin assignments (Figure on page 10 through Figure on page 13) stay

SCC/ESCCUser ManualUM010903-0515 Register Descriptions143This bit enables the Wait/Request function in conjunction with the Request/Wait Function Sele

SCC/ESCCUser ManualUM010903-0515 Register Descriptions144 Z85X30 Register Map READ 8530 85C30/85230W85C30/230* 85C30/230 R15 D2=1A//B PNT2 PNT1 PNT0

SCC/ESCCUser ManualUM010903-0515 Register Descriptions145When programmed to 1, this bit allows the Wait/Request function to follow the state of the re

SCC/ESCCUser ManualUM010903-0515 Register Descriptions146Special receive conditions are: receiver overrun, framing error, end of frame, or parity erro

SCC/ESCCUser ManualUM010903-0515 Register Descriptions147Bit 1: Transmitter Interrupt Enable If this bit is set to 1, the transmitter requests an inte

SCC/ESCCUser ManualUM010903-0515 Register Descriptions148Write Register 3 (Receive Parameters and Control) This register contains the control bits and

SCC/ESCCUser ManualUM010903-0515 Register Descriptions149Bit 5: Auto Enable This bit programs the function for both the /DCD and /CTS pins. /CTS becom

SCC/ESCCUser ManualUM010903-0515 Register Descriptions150The address recognition logic of the receiver is modified in SDLC mode if this bit is set to

SCC/ESCCUser ManualUM010903-0515 Register Descriptions1511X Mode (00). The clock rate and data rate are the same. In External Sync mode, this bit comb

SCC/ESCCUser ManualUM010903-0515 Register Descriptions1521 Stop Bit/Character (01). This bit selects Asynchronous mode with one stop bit per character

SCC/ESCCUser ManualUM010903-0515 General Description9Pin DescriptionsZ80x30 Pin FunctionsAD7AD6AD5AD4AD3AD2AD1AD0/AS/DSR//WCS1/CS0/INT/INTACKIEIIEOTxD

SCC/ESCCUser ManualUM010903-0515 Register Descriptions153These bits control the number of bits in each byte transferred to the transmit buffer. Bits s

SCC/ESCCUser ManualUM010903-0515 Register Descriptions154Bit 2: SDLC/CRC-16 polynomial select bit This bit selects the CRC polynomial used by both the

SCC/ESCCUser ManualUM010903-0515 Register Descriptions155transmit the station address at the beginning of a response frame. Bit positions for WR6 are

SCC/ESCCUser ManualUM010903-0515 Register Descriptions156tion in the section on Write Register 15. Features enabled in WR7 Prime remain enabled unless

SCC/ESCCUser ManualUM010903-0515 Register Descriptions157If WR7' D3=1 and “Receive Interrupt on All Characters and Special Conditions” is enabled

SCC/ESCCUser ManualUM010903-0515 Register Descriptions158Write Register 7 Prime (WR7') Bit 7: Reserved. This bit is reserved and must be programm

SCC/ESCCUser ManualUM010903-0515 Register Descriptions159depending on the speed grade of the device). When this bit is reset to 0, the deactivation ti

SCC/ESCCUser ManualUM010903-0515 Register Descriptions160at the same time as the Reset command, because these bits are only reset by a hardware reset.

SCC/ESCCUser ManualUM010903-0515 Register Descriptions161This bit is reserved on NMOS, and always writes as 0. Bit 4: Status High//Status Low control

SCC/ESCCUser ManualUM010903-0515 Register Descriptions162The Vector Includes Status Bit controls whether or not the SCC includes status information in

SCC/ESCCUser ManualUM010903-0515 General Description10Z85X30 DIP Pin Assignments129345678403938373635343332D0D2D//CD4D6/RD/WRA//B/CED13130292827141011

SCC/ESCCUser ManualUM010903-0515 Register Descriptions163NRZ (NRZI), FM1 (FM0) TimingBit 4: Go-Active-On-Poll control bit When Loop mode is first sele

SCC/ESCCUser ManualUM010903-0515 Register Descriptions164the first data byte is sent to the SCC, but before CRC has been transmitted. If the bit is no

SCC/ESCCUser ManualUM010903-0515 Register Descriptions165mode operation in other registers are set before this mode is selected. The transmitter and r

SCC/ESCCUser ManualUM010903-0515 Register Descriptions166Write Register 11 Bit 7: RTxC-XTAL//NO XTAL select bit This bit controls the type of input si

SCC/ESCCUser ManualUM010903-0515 Register Descriptions167 Bit 2: TRxC Pin I/O control bit This bit determines the direction of the /TRxC pin. If this

SCC/ESCCUser ManualUM010903-0515 Register Descriptions168advisable to disable the baud rate generator while the new time constant is loaded into WR12

SCC/ESCCUser ManualUM010903-0515 Register Descriptions169Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) WR13 contains the upper b

SCC/ESCCUser ManualUM010903-0515 Register Descriptions170Bits D7-D5: Digital Phase-Locked Loop Command Bits. These three bits encode the eight command

SCC/ESCCUser ManualUM010903-0515 Register Descriptions171Set FM Mode Command (110). This command forces the DPLL to operate in the FM mode and is used

SCC/ESCCUser ManualUM010903-0515 Register Descriptions172Bit 3: Auto Echo select bit Setting this bit to 1 selects the Auto Echo mode of operation. In

SCC/ESCCUser ManualUM010903-0515 General Description11Z85X30 PLCC Pin Assignments

SCC/ESCCUser ManualUM010903-0515 Register Descriptions173On the CMOS version, bits D2 and D0 are reserved. On the NMOS version, bit D2 is reserved. Th

SCC/ESCCUser ManualUM010903-0515 Register Descriptions174mation read reflects the current status only. This bit is reset to 0 by a channel or hardware

SCC/ESCCUser ManualUM010903-0515 Register Descriptions175this register. This feature prevents missed status due to changes that take place when the re

SCC/ESCCUser ManualUM010903-0515 Register Descriptions176number of transitions on the /CTS pin causes another External/Status interrupt condition. If

SCC/ESCCUser ManualUM010903-0515 Register Descriptions177If the DCD IE bit in WR15 is set, this bit indicates the state of the /DCD pin the last time

SCC/ESCCUser ManualUM010903-0515 Register Descriptions178Read Register 1 RR1 contains the Special Receive Condition status bits and the residue codes

SCC/ESCCUser ManualUM010903-0515 Register Descriptions179Bit 5: Receiver Overrun Error status This bit indicates that the Receive FIFO has overflowed.

SCC/ESCCUser ManualUM010903-0515 Register Descriptions180Bit 0: All Sent status In Asynchronous mode, this bit is set when all characters have complet

SCC/ESCCUser ManualUM010903-0515 Register Descriptions181Read Register 2 Read Register 3 RR3 is the interrupt Pending register. The status of each of

SCC/ESCCUser ManualUM010903-0515 Register Descriptions182Read Register 4 (ESCC and 85C30 Only) On the ESCC, Read Register 4 reflects the contents of W

SCC/ESCCUser ManualUM010903-0515 General Description12 Z80X30 DIP Pin Assignments 129345678403938373635343332AD0AD2CS1AD4AD6/DS/ASR//W/CS0AD1313029282

SCC/ESCCUser ManualUM010903-0515 Register Descriptions183 Read Register 6 (Not on NMOS) Read Register 7 (Not on NMOS) D7 D6 D5 D4 D3 D2 D1 D0Read Regi

SCC/ESCCUser ManualUM010903-0515 Register Descriptions184 If the FIFO overflows, the FIFO and the FIFO Overflow Status bit are cleared by disabling an

SCC/ESCCUser ManualUM010903-0515 Register Descriptions185Read Register 10 RR10 contains some miscellaneous status bits. Unused bits are always 0. Bit

SCC/ESCCUser ManualUM010903-0515 Register Descriptions186Read Register 11 (ESCC and 85C30 Only) On the ESCC, Read Register 11 reflects the contents of

SCC/ESCCUser ManualUM010903-0515 Register Descriptions187Read Register 13RR13 returns the value stored in WR13, the upper byte of the time constant fo

SCC/ESCCUser ManualUM010903-0515 Application Notes188Application NotesInterfacing Z80® CPUs to the Z8500 Peripheral Family

SCC/ESCCUser ManualUM010903-0515 Application Notes189

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SCC/ESCCUser ManualUM010903-0515iiDO NOT USE IN LIFE SUPPORTLIFE SUPPORT POLICYZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS

SCC/ESCCUser ManualUM010903-0515 General Description13 Z80X30 PLCC Pin AssignmentsPins Common to both Z85X30 and Z80X30 /CTSA, /CTSB. Clear To Send (i

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SCC/ESCCUser ManualUM010903-0515 General Description14is OFF, the /RTS pins are used as general-purpose outputs, and, they strictly follow the inverse

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SCC/ESCCUser ManualUM010903-0515 Application Notes210AN0096: The Z180 Interfaced with the SCC at 10 MHzAbstract This Application Note describes how to

SCC/ESCCUser ManualUM010903-0515 Application Notes211Interfaces The following subsections explain the interfaces between the: •Z180 and Memory •Z180 a

SCC/ESCCUser ManualUM010903-0515 Application Notes212Table on page 212 lists the Z180’s basic timing elements for the opcode’s fetch/memory read/writ

SCC/ESCCUser ManualUM010903-0515 General Description15clock, the clock for the baud rate generator, or the clock for the Digital Phase-Locked Loop. Th

SCC/ESCCUser ManualUM010903-0515 Application Notes213Z180 Memory Read Cycle Timing (One Wait State) EPROM Interface During an Opcode fetch cycle, data

SCC/ESCCUser ManualUM010903-0515 Application Notes214fetch cycle meet specifications, the design satisfies the timing requirements for a memory read c

SCC/ESCCUser ManualUM010903-0515 Application Notes215SRAM Interface Table has timing parameters for 256 kb SRAM for this design.256 kb SRAM Key Timin

SCC/ESCCUser ManualUM010903-0515 Application Notes216No wait states are necessary if there is a 85 ns, or faster, access time by using SRAMs. Since th

SCC/ESCCUser ManualUM010903-0515 Application Notes217Connect the signal Address ANDed together with inactive /IORQ to the /E input. Connect /RD to /OE

SCC/ESCCUser ManualUM010903-0515 Application Notes218Memory Interface LogicPhysical Memory Address Map

SCC/ESCCUser ManualUM010903-0515 Application Notes219Wait State Generator LogicZ180 to I/O Interface The Z180 I/O read/write cycle is similar to the Z

SCC/ESCCUser ManualUM010903-0515 Application Notes220Z180 I/O Write Cycle Timing Z8018010 Timing Parameters for I/O Cycle (Worst Case) Sr. No Symbol P

SCC/ESCCUser ManualUM010903-0515 Application Notes221If you are familiar with the Z80® CPU design, the same interfacing logic applies to the Z180 and

SCC/ESCCUser ManualUM010903-0515 Application Notes222Figure displays a simple address decoder (the required interface signals, other than address dec

SCC/ESCCUser ManualUM010903-0515 General Description16/WR. Write (input, active Low). When the Z85X30 is selected, this signal indicates a write opera

SCC/ESCCUser ManualUM010903-0515 Application Notes223Z180 to SCC Interface The following subsections discuss the various parameters between the Z180/S

SCC/ESCCUser ManualUM010903-0515 Application Notes224Interrupt Control /INTACKInterrupt Acknowledge (input, active Low). This signal shows an Interru

SCC/ESCCUser ManualUM010903-0515 Application Notes225Write Cycle TimingFigure on page 225 displays the SCC Write cycle timing. All register addresses

SCC/ESCCUser ManualUM010903-0515 Application Notes226Z80 Interrupt Daisy-Chain Operation In the Z80 peripherals, both IP and IUS bits control the IEO

SCC/ESCCUser ManualUM010903-0515 Application Notes227SCC Interrupt Status DiagramThe SCC uses /INTACK (Interrupt Acknowledge) for recognition of an in

SCC/ESCCUser ManualUM010903-0515 Application Notes228SCC I/O Read/Write Cycle Assume that the Z180 MPU’s /IOC bit in the OMCR (Operation Mode Control

SCC/ESCCUser ManualUM010903-0515 Application Notes229I/O Read Cycle These tables show that a delay of the falling edge of /RD satisfies the SCC TsA(RD

SCC/ESCCUser ManualUM010903-0515 Application Notes230This circuit depicts logic for the I/O interface and the Interrupt Acknowledge Interface for 10 M

SCC/ESCCUser ManualUM010903-0515 Application Notes231Interrupt Acknowledge Cycle Timing The primary timing differences between the Z180 and SCC occur

SCC/ESCCUser ManualUM010903-0515 Application Notes232During an Interrupt Acknowledge cycle, the SCC requires both /INTACK and /RD to be active at cert

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC17Interfacing the SCC/ESCC Introduction This chapter covers the system interface requirements

SCC/ESCCUser ManualUM010903-0515 Application Notes233Z180 to SCC Interface Logic (Example)T1 T2 Tw T316100 ns112870 ns max55 ns max20 ns max10 ns max1

SCC/ESCCUser ManualUM010903-0515 Application Notes234The primary chip in this logic is the Shift register (HCT164), which generates /INTACK, /SCCRD an

SCC/ESCCUser ManualUM010903-0515 Application Notes235interrupt daisy chain to settle so the device requesting the interrupt places its interrupt vecto

SCC/ESCCUser ManualUM010903-0515 Application Notes236ELPD Circuit ImplementationSystem Checkout After completion of the board (PC board or wire wrappe

SCC/ESCCUser ManualUM010903-0515 Application Notes237Software Considerations Based on the previous discussion, it is necessary to program the Z180 int

SCC/ESCCUser ManualUM010903-0515 Application Notes238(WR0, 38h). A sample program of an SCC Interrupt Test is listed in Table on page 239. It uses th

SCC/ESCCUser ManualUM010903-0515 Application Notes239SCC Test Program – Interrupt for 180/SCC Application Board (Under Mode2 Interrupt) (Continued);*

SCC/ESCCUser ManualUM010903-0515 Application Notes240Table lists a “macro” to enable the Z180 to use the Z80® Assembler, as well as register defini-t

SCC/ESCCUser ManualUM010903-0515 Application Notes241There is one good test to ensure proper function. Generate a data transfer between the Z180/SCC u

SCC/ESCCUser ManualUM010903-0515 Application Notes242Program Example – Z180 CPU Macro Instructions (Continued)bcr1l: equ 2eh ; DMA Byte Count Reg Ch1-

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC18Z80X30 Read CycleZ80X30 Write Cycle Timing The write cycle timing for the Z80X30 is display

SCC/ESCCUser ManualUM010903-0515 Application Notes243Table lists a program example for the Z180/SCC DMA transfer test.Program Example – Z180 CPU Macr

SCC/ESCCUser ManualUM010903-0515 Application Notes244.Test Program–Z180/SCC DMA Transfer

SCC/ESCCUser ManualUM010903-0515 Application Notes245Test Program–Z180/SCC DMA Transfer (Continued)call initdmald b,0 ;init statusld a,00h ;load 1st d

SCC/ESCCUser ManualUM010903-0515 Application Notes246Test Program–Z180/SCC DMA Transfer (Continued)initscc: ld hl,scctab ; initialize sccinit0: ld a,(

SCC/ESCCUser ManualUM010903-0515 Application Notes247Test Program–Z180/SCC DMA Transfer (Continued)db 01h ;select WR1db 01100000b ;REQ on Rxdb 02h ;se

SCC/ESCCUser ManualUM010903-0515 Application Notes248Test Program–Z180/SCC DMA Transfer (Continued)db 01h ;select WR1db 11100000b ;enable DMAdb 0fh ;s

SCC/ESCCUser ManualUM010903-0515 Application Notes249First, this program (Table on page 244) initializes the SCC by Async, X1 mode, 8-bit 1 stop, Non

SCC/ESCCUser ManualUM010903-0515 Application Notes250AN0097: The Zilog® Datacom Family with the 80186 CPUAbstractZilog’s customers need a way to evalu

SCC/ESCCUser ManualUM010903-0515 Application Notes251Table lists the conventional descriptions for the power connections.ProcessorThe 80186 CPU can o

SCC/ESCCUser ManualUM010903-0515 Application Notes252The ISCC and IUSC handle their own DMA transfers through the 80186’s HOLD/HLDA facility.Either a

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC19Z80X30 Write Cycle Z80X30 Interrupt Acknowledge Cycle Timing The interrupt acknowledge cycl

SCC/ESCCUser ManualUM010903-0515 Application Notes253Push button switches are provided for Reset and Non-Maskable Interrupt (NMI). A method to genera

SCC/ESCCUser ManualUM010903-0515 Application Notes254J18 connects Pin 1 of both sockets to either A16 or VCC. For 2764s, 27128s, and 27256s, Pin 1 is

SCC/ESCCUser ManualUM010903-0515 Application Notes255J19 is factory set according to the size of the SRAMs provided. For 32K x 8 SRAMs, jumpers are in

SCC/ESCCUser ManualUM010903-0515 Application Notes256The three LSBs of the PACs value specify the Ready/WAIT handling for the PCS3-PCS0 lines which se

SCC/ESCCUser ManualUM010903-0515 Application Notes257Interrupt Daisy Chain (Priority) OrderJumper block J25 selects whether the (E)SCC device is at th

SCC/ESCCUser ManualUM010903-0515 Application Notes258as the speeds possible with a DMA approach. To use the W/REQB output as a Receive DMA Request, ju

SCC/ESCCUser ManualUM010903-0515 Application Notes259Then, the basic register map occurs twice in the even addresses from (PBA) through (PBA)+126 as l

SCC/ESCCUser ManualUM010903-0515 Application Notes260•The MSB of the data (D7) is 1 to enable the Byte Swap feature, so that when the ISCC’s DMA contr

SCC/ESCCUser ManualUM010903-0515 Application Notes261Jumper block J29 provides the same connection-variability for the RxREQ and TxREQ outputs of Chan

SCC/ESCCUser ManualUM010903-0515 Application Notes262While the ESCC and ISCC drive their Baud Rate Generators from their PCLK inputs, the (M)USC has n

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC20Z80X30 Interrupt Acknowledge CycleThe Z80X30 samples the state of /INTACK on the rising edg

SCC/ESCCUser ManualUM010903-0515 Application Notes263•D7-D6 are 11 to allow the DMA controllers to do either 16-bit transfers, or alternating byte tra

SCC/ESCCUser ManualUM010903-0515 Application Notes264can be interconnected for communication between on-board serial controllers, or they can be con-n

SCC/ESCCUser ManualUM010903-0515 Application Notes265The ground pins are included as signal references with off-board hardware. When interconnecting b

SCC/ESCCUser ManualUM010903-0515 Application Notes266Comparison of the two previous tables leads to following conclusions:•Pins 1-5 can always be jump

SCC/ESCCUser ManualUM010903-0515 Application Notes267Finally, an unpopulated 4-pin oscillator socket is included on the board with its output connecte

SCC/ESCCUser ManualUM010903-0515 Application Notes268If none of the allowed serial channels produce an NMI, you may not have properly jumpered any J5-

SCC/ESCCUser ManualUM010903-0515 Application Notes269pin is driven from the same signal as CTS. To be compatible with this feature, connect J15-J4 to

SCC/ESCCUser ManualUM010903-0515 Application Notes270J23-J1 thru -3 1 to 2: (E)SCC B RxRQ on DMA 02 to 3: (E)SCC B Wait function(E)SCC B neither RxD

SCC/ESCCUser ManualUM010903-0515 Application Notes271Control EPLD for 186 Board

SCC/ESCCUser ManualUM010903-0515 Application Notes272SCC EPLD for 186 Board

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC21If there is an interrupt pending in the SCC, and IEI is High when /DS falls, the acknowl-ed

SCC/ESCCUser ManualUM010903-0515 Application Notes273DMA EPLD for 186 Board

SCC/ESCCUser ManualUM010903-0515 Application Notes274NMI Field for 186 Board

SCC/ESCCUser ManualUM010903-0515275SCC in Binary Synchronous Communications

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SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC220 0 0 1 0 WR2 RR2B RR2B RR2B 0 0 0 1 1 WR3B RR3B RR3B RR3B0 0 1 0 0 WR4B (RR0B) (RR0B) (WR4

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SCC/ESCCUser ManualUM010903-0515iiiRevision HistoryEach instance in Revision History reflects a change to this document from its previous revision. Fo

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC231 1 1 0 1 WR13A RR13A RR13A RR13A1 1 1 1 0 WR14A RR14A RR14A (WR7’A)1 1 1 1 1 WR15A RR15A R

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SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC24Z80C30 Register Enhancement The Z80C30 has an enhancement to the NMOS Z8030 register set, w

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SCC/ESCCUser ManualUM010903-0515311AN0300: Boost Your System Performance Using the Zilog ESCC Controller

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SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC25Z80230 Register Enhancements In addition to the Z80C30 enhancements, the 80230 has several

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SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC26Z80X30 ResetThe Z80X30 may be reset by either a hardware or software reset. Hardware reset

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SCC/ESCCUser ManualUM010903-0515325AN006: Technical Considerations When Implementing Localtalk Link Access Protocol

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SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC27Z85X30 Interface Timing Two control signals, /RD and /WR, are used by the Z85X30 to time bu

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SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC28Z85X30 Read Cycle Timing The read cycle timing for the Z85X30 is displayed in Figure on pa

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SCC/ESCCUser ManualUM010903-0515344AN0075: On-Chip Oscillator Design

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SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC29 Z85X30 Write Cycle TimingZ85X30 Interrupt Acknowledge Cycle Timing The interrupt acknowled

SCC/ESCCUser ManualUM010903-0515353Interfacing the ISCC to the 68000 and 8086

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SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC30Between the time /INTACK is first sampled Low and the time /RD falls, the internal and exte

SCC/ESCCUser ManualUM010903-0515363Zilog SCC Z8030/Z8530 Questions and Answers

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SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC31There are three pointer bits in WR0, and these allow access to the registers with addresses

SCC/ESCCUser ManualUM010903-0515373Zilog ESCC Controller Questions and Answers

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SCC/ESCCUser ManualUM010903-0515 Questions and Answers375Questions and AnswersZilog SCC Z8030/Z8530 Questions and Answers

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SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC32Z85C30 Register Enhancement The Z85C30 has an enhancement to the NMOS Z8530 register set, w

SCC/ESCCUser ManualUM010903-0515 Questions and Answers383

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SCC/ESCCUser ManualUM010903-0515 Questions and Answers385Zilog ESCC Controller Questions and Answers

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SCC/ESCCUser ManualUM010903-0515 Customer Support387Customer SupportFor answers to technical questions about the product, documentation, or any other

SCC/ESCCUser ManualUM010903-0515ivTable of ContentsGeneral Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC33for the 85230/L, while Figure on page 29 displays the register bit location for the 85C30.

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC34Setting WR7' bit D6=1 enables the extended read register capability. This allows the u

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC35 Interface Programming The following subsections explain and illustrate all areas of interf

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC36I/O Programming Introduction The SCC can work with three basic forms of I/O operations: pol

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC37ESCC Interrupt SourcesESCC:The receive interrupt request is either caused by a receive char

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC38D3. If WR7' D3=0, the receive character available interrupt is generated when one char

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC39Peripheral Interrupt Structure Figure displays the internal priority resolution method to

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC40Master Interrupt Enable Bit The Master Interrupt Enable (MIE) bit, WR9 D3, must be set to e

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC41IUS bits can be set by either a hardware acknowledge cycle with the /INTACK pin or through

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC42•IP is set without a higher priority IUS being set •No higher priority IUS is being set •No

SCC/ESCCUser ManualUM010903-0515vExternal/Status Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Block/DMA Tran

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC43some action taken by the processor. The external daisy chain may be controlled by the DLC b

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC44Interrupt Acknowledge The SCC is flexible with its interrupt method. The interrupt may be a

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC45cuted internally. Like a hardware INTACK cycle, a software acknowledge causes the /INT pin

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC46response time can use this mode to generate an interrupt when one byte is received, but sti

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC47When these bits indicate that a received character has reached the exit location of the FIF

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC48the receive data FIFO so that the service routine must read the status in RR1 before readin

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC49unlock it. Only the exit location of the FIFO is locked allowing more data to be received i

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC50empty. Transmit interrupts should also be disabled in the case of DMA transfer of the trans

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC51When WR7' D5=1 (the default case), the ESCC will generate a transmit interrupt when th

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC52An enhancement to the ESCC from the NMOS/CMOS version is that the CRC has priority over the

SCC/ESCCUser ManualUM010903-0515viWrite Register 1 (Transmit/Receive Interrupt and Data Transfer Mode Definition) . . . . . . . . . . . . . . . . .

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC53 Transmit Buffer Empty Bit Status For ESCC For Both WR7' and WR7' D5=0 Transmit I

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC54data written. On the ESCC, the CRC has priority over the data. That means after the recepti

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC55An example flowchart for processing an end of packet is displayed in Figure . The chart inc

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC56External/Status Interrupts Each channel has six external/status interrupt conditions: BRG Z

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC57are closed. If the master enable for the External/Status interrupts is not set, the IP is n

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC58twice to detect changes that otherwise may be missed. The contents of RR0 are latched on th

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC59CTS/DCD The CTS bit reports the state of the /CTS input, and the DCD bit reports the status

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC60Block/DMA Transfer The SCC provides a Block Transfer mode to accommodate CPU block transfer

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC61Wait On Transmit TimingThis allows the use of a block move instruction to transfer the tran

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC62Wait On ReceiveThe Wait On Receive function is selected by setting D6 or WR1 to 0, D5 of WR

SCC/ESCCUser ManualUM010903-0515viiSCC in Binary Synchronous Communications . . . . . . . . . . . . . . . . . . . . . . 275Serial Communication Con

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC63Care must be taken when this mode is used. The /WAIT pin stays active as long as the Receiv

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC64DMA Request On Transmit (using /W//REQ) The Request On Transmit function is selected by set

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC65With only one exception, the /REQ pin directly follows the state of the transmit buffer (fo

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC66DMA Request On Transmit (using /DTR//REQ) A second Request on Transmit function is availabl

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC67If WR7' D4=1, analysis should be done to verify that the ESCC is not repeatedly access

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC68from the time the character with the special receive condition is read, and the FIFO locked

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC69Z85X30 Receive Request ReleaseTest Functions The SCC contains two other features useful for

SCC/ESCCUser ManualUM010903-0515 Interfacing the SCC/ESCC70but both the /CTS pin and /DCD pin are ignored as auto enables. This should not be consider

SCC/ESCCUser ManualUM010903-0515 SCC/ESCC Ancillary Support Circuitry71SCC/ESCC Ancillary Support Circuitry Introduction The serial channels of the SC

SCC/ESCCUser ManualUM010903-0515 SCC/ESCC Ancillary Support Circuitry72over. The programmed time constant is read from RR12 and RR13. A block diagram

SCC/ESCCUser ManualUM010903-0515 General Description1General DescriptionIntroduction Zilog’s SCC Serial Communication Controller is a dual channel, mu

SCC/ESCCUser ManualUM010903-0515 SCC/ESCC Ancillary Support Circuitry73The BRG is enabled while bit D0 of WR14 is set to 1. It is disabled while WR14

SCC/ESCCUser ManualUM010903-0515 SCC/ESCC Ancillary Support Circuitry74. Other commonly used clock frequencies include 3.6846, 4.6080, 4.91520, 6.144,

SCC/ESCCUser ManualUM010903-0515 SCC/ESCC Ancillary Support Circuitry75synchronous. The data encoding selected is active even though the transmitter o

SCC/ESCCUser ManualUM010903-0515 SCC/ESCC Ancillary Support Circuitry76forced High on the falling edge of the TxC cycle after the falling edge of the

SCC/ESCCUser ManualUM010903-0515 SCC/ESCC Ancillary Support Circuitry77Figure on page 75, the transmitter defines bit cell boundaries by one edge in

SCC/ESCCUser ManualUM010903-0515 SCC/ESCC Ancillary Support Circuitry78DPLL Digital Phase-Locked Loop Each channel of the SCC contains a digital phase

SCC/ESCCUser ManualUM010903-0515 SCC/ESCC Ancillary Support Circuitry79WR14 (7-5) = 110 selects FM modeA channel or hardware reset disables the DPLL,

SCC/ESCCUser ManualUM010903-0515 SCC/ESCC Ancillary Support Circuitry80the next 0 to 31 counting cycle, which effectively moves the edge of the clock

SCC/ESCCUser ManualUM010903-0515 SCC/ESCC Ancillary Support Circuitry81DPLL Operation in the FM Modes To operate in FM mode, the DPLL must be supplied

SCC/ESCCUser ManualUM010903-0515 SCC/ESCC Ancillary Support Circuitry82If no transition occurs between the middle of count 12 and the middle of count

SCC/ESCCUser ManualUM010903-0515 General Description2NMOS: Description applies to NMOS version (Z8030/Z8530)CMOS: Description applies to CMOS version

SCC/ESCCUser ManualUM010903-0515 SCC/ESCC Ancillary Support Circuitry83Transmit Clock Counter (ESCC only) The ESCC includes a Transmit Clock Counter w

SCC/ESCCUser ManualUM010903-0515 SCC/ESCC Ancillary Support Circuitry84Ordinarily, the /TRxC pin is an input, but it can become an output if this pin

SCC/ESCCUser ManualUM010903-0515 SCC/ESCC Ancillary Support Circuitry85Clock MultiplexerAsync Clock Setup Using an External CrystalOSC/SYNC/RTxCOSCRec

SCC/ESCCUser ManualUM010903-0515 SCC/ESCC Ancillary Support Circuitry86Clock Source Selection Figure on page 87 displays the use of the DPLL to deriv

SCC/ESCCUser ManualUM010903-0515 SCC/ESCC Ancillary Support Circuitry87Synchronous Transmission, 1x Clock Rate, FM Data Encoding, using DPLLCrystal Os

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes88Data Communication Modes Introduction The SCC provides two independent, full-duplex channel

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes89nous modes, the SDLC flag character (7E hex) is programmed in WR7 and is loaded into the Tr

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes90to enable the Receive FIFO, since it is available in all modes of operation. For each data

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes91character programmed in WR7 and the character assembled in the Receive Sync register to est

SCC/ESCCUser ManualUM010903-0515 Data Communication Modes92Asynchronous Mode In asynchronous communications, data is transferred in the format display