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SCC/ESCC
User Manual
UM010903-0515 Application Notes
261
Jumper block J29 provides the same connection-variability for the RxREQ and TxREQ outputs of
Channel B of a USC.
Since the 80186’s channels are not capable of fly-by operation, the (M)USC’s RxACK
and
TxACK
pins have no dedicated function. They can be used for Request to Send and Data Terminal
Ready. The two signals are lightly pulled up since they are not driven after Reset.
The (M)USC can be programmed using 16-bit data on the AD15-AD0 lines or 8-bit data on
AD15-AD8 and AD7-AD0. It makes the distinction between 8-bit and 16-bit operations as part of
its address map rather than through a control input. The PS pin of an MUSC, or the A/B
pin of a
USC, is connected to a latched version of the 80186 A7. The D/C
pin of the (M)USC is grounded.
The overall address range of the (M)USC is 256 Bytes, between (PBA)+256 and (PBA)+511.
The first write to this address range, after a Reset, implicitly writes the (M)USC Bus Configura-
tion Register (BCR). To match the rest of the board’s hardware, the first write must be 16-bit write,
storing the hex value 0007 at any address in the second half of the (M)USC’s range [any address
in (PBA)+384 through 510, that is, in the A channel of a USC]. Details of this transaction are as
follows:
•
The High on the PS or A/B input, which is connected to A7, selects the WAIT protocol on
the WAIT
/RDY pin, corresponding to how the 80186 works.
•
The MSB of the data (D15) is 0 because a separate non-multiplexed address is not wired to
pins AD13:8 of the (M)USC.
•
Bits 14-3 are required to be all zeros by the (M)USC internal logic.
•
D2 of the data is 1 to tell the (M)USC that the data bus is 16 bits wide.
•
D1 of the data is 1 to select double-pulsed mode for the (M)USC’s INTACK input. This is
how the 80186 CPU functions.
•
D0 of the data is 1 to select Shift Right Address mode so that the (M)USC subsequently
takes register addressing from the AD6-AD0 lines rather than from AD7-AD1.
•
The fact that the (M)USC’s internal logic sees activity on its AS pin, which is inverted
from the 80186’ ALE signal, automatically conditions it for a multiplexed Addresses/Data
bus.
Given that the BCR is written as described above, the (M)USC address map is as listed in Table .
(M)USC Address Map
Starting Address Ending Address Registers Accessed
(PBA)+256 (PBA)+319 16-bit access to (M)USC registers or USC Channel B Registers
(PBA)+320 (PBA)+383 8-bit access to (M)USC registers or USC Channel B Registers
(PBA)+384 (PBA)+447 16-bit access to (M)USC registers or USC Channel A Registers
- SCC/ESCC 1
- UM010903-0515 2
- Revision History 3
- Table of Contents 4
- SCC’s Capabilities 9
- User Manual 13
- SCC Block Diagram 13
- Pin Descriptions 14
- Z85X30 DIP Pin Assignments 17
- Z85X30 PLCC Pin Assignments 18
- Z80X30 DIP Pin Assignments 19
- Interfacing the SCC/ESCC 24
- Z80X30 Write Cycle Timing 25
- Z80X30 Register Access 28
- Z80C30 Register Enhancement 31
- Z80230 Register Enhancements 32
- Z80X30 Reset 33
- Z85X30 Interface Timing 34
- Z85X30 Read Cycle Timing 35
- Z85X30 Write Cycle Timing 35
- D7-D0 Vector 36
- Z85X30 Register Access 37
- Z85C30 Register Enhancement 39
- Z85X30 Reset 41
- Interface Programming 42
- I/O Programming Introduction 43
- Interrupts 43
- External/Status Channel A 44
- Receive Channel B 44
- Transmit Channel B 44
- * Always 0 In B Channel 47
- Daisy-Chain Resolution 48
- Interrupt Acknowledge 51
- The Receiver Interrupt 52
- Receive Interrupts Disabled 53
- Conditio 56
- External/Status Interrupts 63
- Break/Abort 65
- Transmit Underrun/EOM 65
- CTS/DCD 66
- Zero Count 66
- Sync/Hunt 66
- Block/DMA Transfer 67
- SYNC Modes 68
- ASYNC Modes 68
- Wait On Receive 69
- DMA Requests 70
- DMA Request On Receive 74
- AD7-AD0 Receive DataWR8 75
- Test Functions 76
- Introduction 78
- Baud Rate Generator 78
- Data Encoding/Decoding 81
- Clock Selection 90
- Clock Multiplexer 92
- BRG Clock Source = /RTXC 93
- Crystal Oscillator 94
- Data Communication Modes 95
- Transmit Data Path 96
- Asynchronous Mode 99
- Asynchronous Transmit 100
- Asynchronous Receive 103
- Asynchronous Initialization 105
- Reg Bit No Description 107
- WR4 3 (=0) select sync mode 107
- State Changes in One 113
- /RTxC Clock Cycle 113
- SDLC Transmit 121
- SDLC Receive 127
- SDLC Frame Status FIFO 133
- Frame Status FIFO Circuitr 135
- Interface 135
- SDLC Loop Mode 137
- SDLC Loop Mode Receive 140
- SDLC Loop Mode Transmit 140
- Register Descriptions 143
- Write Registers 145
- Definition) 149
- Z85X30 Register Map 151
- Time Constant 175
- Clock Frequency 175
- Read Registers 181
- Read Register 1 185
- Read Register 2 187
- Read Register 3 188
- Read Register 8 191
- Read Register 10 192
- Read Register 12 193
- Read Register 13 194
- Read Register 15 194
- Application Notes 195
- Abstract 217
- Features 217
- Discussion 217
- Interfaces 218
- Z180 to Memory Interface 218
- EPROM Interface 220
- SRAM Interface 222
- SRAM Read Cycle 222
- SRAM Write Cycle 223
- Memory Interface Logic 223
- Physical Memory Address Map 225
- Z180 to I/O Interface 226
- Z180 I/O Write Cycle Timing 227
- Z180 to SCC Interface 230
- CPU Hardware Interfacing 230
- Data Bus Signals 230
- System Control Signals 230
- Interrupt Control 231
- SCC I/O Operation 231
- Read Cycle Timing 231
- Write Cycle Timing 232
- SCC Interrupt Operation 232
- Input/Output Cycles 234
- Z180 MPU to SCC Interface 234
- SCC I/O Read/Write Cycle 235
- I/O Read Cycle 235
- I/O Write Cycle 235
- Using EPLD 242
- System Checkout 243
- Software Considerations 244
- SCC Read Cycle Proof 244
- SCC Write Cycle Proof 244
- Interrupt Acknowledge Cycle 244
- (Continued) 246
- Summary 256
- General Description 257
- Processor 258
- Address Map 260
- (PBA)+511 269
- Serial Interfacing 270
- DMA channel 272
- Jumper Summary 276
- Control EPLD for 186 Board 278
- SCC EPLD for 186 Board 279
- DMA EPLD for 186 Board 280
- NMI Field for 186 Board 281
- Operation 295
- ESCC Controller 318
- Questions and Answers 382
- Customer Support 394
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