Zilog Z16C35 Uživatelský manuál

Copyright © 2008 by Zilog®, Inc. All rights reserved.www.zilog.comUM011002-0808User Manual Z16C35ISCC

ISCCUser ManualUM011002-08084Figure 1–2. Pin FunctionsPage 4 of 316

ISCCUser ManualUM011002-0808945.4.2 Write Register 1 (Transmit/Receive Interrupt and Data Transfer Mode Definition) Write Register 1 is the control r

ISCCUser ManualUM011002-080895Figure 5–32. Write Register 10 011 WR11B (RR15B) 0 100 WR12B RR12B 0 101 WR13B RR13B 0 110 WR14

ISCCUser ManualUM011002-080896Bit 7, 6, and 5 are not used in the ISCC. These bits were used in the SCC cell to control the action of the /WAIT//REQUE

ISCCUser ManualUM011002-080897Bit 2 selects Parity Is Special Condition If this bit is set to “1,” any received characters with parity not matching th

ISCCUser ManualUM011002-0808985.4.4 Write Register 3 (Receive Parameters and Control) This register contains the control bits and parameters for the

ISCCUser ManualUM011002-080899Bit 5 selects Auto Enables This bit programs the function for both the /DCD and /CTS pins. /CTS becomes the trans-mitter

ISCCUser ManualUM011002-0808100If the 6-bit sync option is selected with this bit set to “1,” all sync characters except the one immediately preceding

ISCCUser ManualUM011002-0808101Bit 7 and 6 are the Clock Mode, Bits 1 And 0 These bits specify the multiplier between the clock and data rates. In syn

ISCCUser ManualUM011002-0808102transmitter is in Monosync mode using the contents of WR6 as the time fill with the sync character length specified by

ISCCUser ManualUM011002-08081035.4.6 Write Register 5 (Transmit Parameter and Controls) WR5 contains control bits that affect the operation of the tr

ISCCUser ManualUM011002-08085Figure 1–3. Pin AssignmentsISCCZ16C3510111213141516171819202122232425266059585756555453525150494847464544IEO/INT/SYNCA/RT

ISCCUser ManualUM011002-0808104For five or less bits per character selection in WR5, the following encoding is used in the data sent to the transmitte

ISCCUser ManualUM011002-0808105 Figure 5–37. Write Register 65.4.8 Write Register 7 (SYNC Character or SDLC Flag) WR7 is programmed to contain the re

ISCCUser ManualUM011002-08081065.4.9 Write Register 8 (Transmit Buffer) WR8 is the transmit buffer register. 5.4.10 Write Register 9 (Master Interru

ISCCUser ManualUM011002-0808107Bit combination 01 is the Channel Reset B Command. Issuing this command causes a channel reset to be performed on Chann

ISCCUser ManualUM011002-0808108daisy-chain from requesting interrupts. This bit is reset by a hardware reset. (Note that in the ISCC this will also pr

ISCCUser ManualUM011002-0808109Bit 7 is the CRC Presets 1//0 select bit This bit specifies the initialized condition of the receive CRC checker and th

ISCCUser ManualUM011002-0808110Bit 4 is the Go Active On Poll control bit When Loop mode is first selected during SDLC operation, the ISCC connects Rx

ISCCUser ManualUM011002-0808111transmitted after the transmit underrun. This bit should be set after the first byte of data is sent to the ISCC and re

ISCCUser ManualUM011002-08081125.4.12 Write Register 11 (Clock Mode Control)WR11 is the Clock Mode Control Register. The bits in this register contro

ISCCUser ManualUM011002-0808113plexer just before the internal receive clock input. A hardware reset forces the receive clock to come from the /RTxC p

ISCCUser ManualUM011002-080861.3 Pin DescriptionThe following section describes the Z16C35 pin functions. Figures 1-2 and 1-3 detail the respective p

ISCCUser ManualUM011002-0808114If the XTAL oscillator output is programmed to be echoed, and the XTAL oscillator has not been enabled, the /TRxC pin g

ISCCUser ManualUM011002-0808115Figure 5–43. Write Register 125.4.14 Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) WR13 contains

ISCCUser ManualUM011002-08081165.4.15 Write Register 14 (Miscellaneous Control Bits) WR14 contains some miscellaneous control bits. Bit positions for

ISCCUser ManualUM011002-0808117first data edge. Beyond this point, the DPLL begins normal operation, adjusting the output to remain in sync with the i

ISCCUser ManualUM011002-0808118works with any Transmit/Receive mode except Loop mode. For meaningful results, the frequency of the transmit and receiv

ISCCUser ManualUM011002-0808119bit are sent to “1” will cause an interrupt. This is true, even if an External/Status condition is pending at the time

ISCCUser ManualUM011002-0808120If this bit is set to “1,” an External/Status interrupt is generated whenever the counter in the baud rate generator re

ISCCUser ManualUM011002-0808121(seven or more “1s”), then reset automatically at the termination of the Abort sequence. In either case, if the Break/A

ISCCUser ManualUM011002-0808122been lost or that a new message is about to start. Both transitions on the /SYNC pin cause External/Status interrupts i

ISCCUser ManualUM011002-0808123External/Status conditions for changes. If none changed, Zero Count was the source. In polled applications, check the I

ISCCUser ManualUM011002-08087Configuration Register (BCR). The double pulse acknowledge is compatible with 8X86 family microprocessors. PCLK. Clock (i

ISCCUser ManualUM011002-0808124the next character is received. When used for CRC error status in Synchronous or SDLC modes, this bit is usually set si

ISCCUser ManualUM011002-0808125Bit 0 is the All Sent status In Asynchronous mode, this bit is set when all characters have completely cleared the tran

ISCCUser ManualUM011002-0808126Figure 5–49. Read Register 25.5.4 Read Register 3 RR3 is the interrupt Pending register. The status of each of the int

ISCCUser ManualUM011002-08081275.5.5 Read Register 8 RR8 is the Receive Data register. 5.5.6 Read Register 10 RR10 contains some miscellaneous statu

ISCCUser ManualUM011002-0808128This bit can be polled in SDLC mode to determine when the closing flag has been sent. Bit 1 is the On Loop status This

ISCCUser ManualUM011002-0808129Figure 5–53. Read Register 135.5.9 Read Register 15RR15 reflects the value stored in WR15, the External/Status IE bits

ISCCUser ManualUM011002-08081305.6 DMA CELL REGISTER DESCRIPTIONS 5.6.1 Channel Command/Address Register This register is a write only register and

ISCCUser ManualUM011002-0808131Bit combination 110 is the command to enable the Transmitter A channel DMA. The DMA operation is not triggered by this

ISCCUser ManualUM011002-0808132Bit 2, when set, indicates that the Transmitter A DMA operation has been aborted. Bit 1, when set, indicates that the R

ISCCUser ManualUM011002-0808133bit is set). This status information is contained in bits 1, 2, and 3 of the interrupt vector. The other interrupt vect

ISCCUser ManualUM011002-08088Phase-Locked Loop, the crystal oscillator, the baud rate generator, or the transmit clock in the output mode. /CE. Chip E

ISCCUser ManualUM011002-08081343 may be replaced by interrupt status information if the Vector Include Status option has been selected (see Interrupt

ISCCUser ManualUM011002-08081355.6.5 Interrupt Command Register This is a write only register and is used to command the DMA cell. It shares its addr

ISCCUser ManualUM011002-0808136Bit 4 is Reserved. (This bit should be programmed as a zero to avoid conflicts with future versions of this device.) Bi

ISCCUser ManualUM011002-0808137Bit 6 reflects the Transmit A DMA Interrupt Under Service status. The function of this bit is identical to that for bit

ISCCUser ManualUM011002-0808138Bit 7, when set to 1, enables the Receive A DMA. Bit 6, when set to 1, enables the Transmit A DMA. Bit 5, when set to 1

ISCCUser ManualUM011002-0808139requests pending, thus multiple channels may make DMA transfers without separate, intervening bus acquisitions. Bit 6 i

ISCCUser ManualUM011002-0808140 Figure 5–63. Receive DMA Count Registers5.6.10 Transmit DMA Count Registers A, B There are two sets of Transmit DMA C

ISCCUser ManualUM011002-0808141 Figure 5–64. Transmit DMA Count Registers5.6.11 Receive DMA Address Registers A, B There are two sets of Receive DMA

ISCCUser ManualUM011002-0808142Figure 5–65. Receive DMA Address Registers(A)Address: 10000 (Bits 0-7)D6D7D5 D4 D3 D2 D1 D0Rx A Addr0Rx A Addr1Rx A Add

ISCCUser ManualUM011002-0808143Figure 5-36. Received DMA Address Registers (Continued)5.6.12 Transmit DMA Address Registers A, B There are two sets o

ISCCUser ManualUM011002-08089from the addressed location or device, and Write (low) indicating that data is being pre-sented to the addressed location

ISCCUser ManualUM011002-0808144Figure 5–66. Transmit DMA Address Registers(A)Address: 10100 (Bits 0-7)D6D7D5 D4 D3 D2 D1 D0Tx A Addr0Tx A Addr1Tx A Ad

ISCCUser ManualUM011002-0808145Figure 5–67. Transmit DMA Address Registers (Continued)5.6.13 Bus Configuration Register The first write to the ISCC a

ISCCUser ManualUM011002-0808146 Figure 5–68. Bus Configuration RegisterBit D7 is the Byte Swap Enable A zero in this bit disables the byte swap featur

ISCCUser ManualUM011002-0808147Bits D2 and D1 program the Interrupt acknowledge type according to Table 5-16.The Status Acknowledge is compatible with

ISCCUser ManualUM011002-0808148Customer SupportFor answers to technical questions about the product, documentation, or any other issues with Zilog’s

6 6 A PPLICATION N OTE I NTERFACING Z80 ® CPU S TO THE Z8500 P ERIPHERAL F AMILY 6 INTRODUCTION The Z8500 Family consists of universal perip

Application Note Interfacing Z80 ® CPUs to the Z8500 Peripheral Family 6-2 CPU HARDWARE INTERFACING (Continued) Z80 ® Interrupt Daisy-Chain Opera

Application Note Interfacing Z80 ® CPUs to the Z8500 Peripheral Family 6-3 6 Write Cycle Timing Figure 2 illustrates the Z8500 Write cycle timing. A

Application Note Interfacing Z80 ® CPUs to the Z8500 Peripheral Family 6-4 PERIPHERAL INTERRUPT OPERATION Understanding peripheral interrupt operati

Application Note Interfacing Z80 ® CPUs to the Z8500 Peripheral Family 6-5 6 INPUT/OUTPUT CYCLES Although Z8500 peripherals are designed to be asuni

ISCCUser ManualUM011002-080810A1/A//B. DMA Channel/Channel A/Channel B (bidirectional). This signal, when used as input, selects the SCC channel in wh

Application Note Interfacing Z80 ® CPUs to the Z8500 Peripheral Family 6-6 INPUT/OUTPUT CYCLES (Continued) . Table 2. Z8500 Timing Parameters I/O

6 Figure 4. Z80A CPU to Z8500 Peripheral Minimum I/O Cycle TimingApplication Note Interfacing Z80 ® CPUs to the Z8500 Peripheral Family Interfacin

Application Note Interfacing Z80 ® CPUs to the Z8500 Peripheral Family 6-8 Z80B CPU TO Z8500A PERIPHERALS No additional Wait states are necessary du

Application Note Interfacing Z80 ® CPUs to the Z8500 Peripheral Family 6-6 INPUT/OUTPUT CYCLES (Continued) . Table 2. Z8500 Timing Parameters I/O

Application NoteInterfacing Z80 ® CPUs to the Z8500 Peripheral Family 6 Z90H CPU TO Z8500 PERIPHERALS During an I/O Read cycle, there are three Z8

6-11 6 Figure 6. Z80H CPU to Z8500 Peripheral Minimum I/O Cycle Timing Interfacing Z80 ® CPUs to the Z8500 Peripheral FamilyPage 159 of 316UM011002-

6-12 Z80H CPU TO Z8500A PERIPHERALS During an I/O Read cycle, there are three Z8500Aparameters that must be satisfied. Depending upon theloading char

6-136Figure 7. Z80H CPU to Z8500A Peripheral Minimum I/O Cycle Timing Application Note Interfacing Z80 ® CPUs to the Z8500 Peripheral FamilyPage 161

Application NoteInterfacing Z80® CPUs to the Z8500 Peripheral Family6-14 Z80H CPU TO Z8500A PERIPHERALS (Continued)Figure 8. Delaying /RD or /WRTable

Application NoteInterfacing Z80® CPUs to the Z8500 Peripheral Family6-156INTERRUPT ACKNOWLEDGE CYCLESThe primary timing differences between the Z80 CP

ISCCUser ManualUM011002-080811Chapter 2 Interfacing the ISCC™2.1 IntroductionThis chapter details the interfacing of the 16C35 ISCC to a system. Cov

Application NoteInterfacing Z80® CPUs to the Z8500 Peripheral Family6-16 EXTERNAL INTERFACE LOGIC (Continued)During I/O and normal memory access cycle

Application NoteInterfacing Z80® CPUs to the Z8500 Peripheral Family6-176Z8500/Z8500A PeripheralsFigure 11 depicts logic that can be used in interfaci

Application NoteInterfacing Z80® CPUs to the Z8500 Peripheral Family6-18 EXTERNAL INTERFACE LOGIC (Continued)During RETI cycles, the IEO line from the

Application NoteInterfacing Z80® CPUs to the Z8500 Peripheral Family6Figure 12. Z80H CPU to Z8500 Peripheral Interrupt Acknowledge Interface TimingFig

Application NoteInterfacing Z80® CPUs to the Z8500 Peripheral Family EXTERNAL INTERFACE LOGIC (Continued)Figure 14. Z80 and Z8500 Peripheral Interrupt

Application NoteInterfacing Z80® CPUs to the Z8500 Peripheral Family6Figure 15. Z80 and Z8500 Peripheral Interrupt Acknowledge Interface TimingPage 16

Application NoteInterfacing Z80® CPUs to the Z8500 Peripheral FamilySOFTWARE CONSIDERATIONS - POLLED OPERATIONThere are several options available for

Application NoteInterfacing Z80® CPUs to the Z8500 Peripheral Family6A SIMPLE Z80-Z8500 SYSTEMThe Z8500 devices interface easily to the Z80 CPU, thusp

7-1 7 A PPLICATION N OTE T HE Z180 ™ I NTERFACED WITH THE SCC AT MHZ 7 uild a simple system to prove and test the Z180 MPU interfacing the

Application Note The Z180™ Interfaced with the SCC at MHZ 7-2 INTERFACES The following subsections explain the interfaces betweenthe: Z180 and Memo

ISCCUser ManualUM011002-080812ter (CSAR bits 4 - 0). The SCC cell and DMA cell pointers are independent. Detailed operation is described in a later se

Application Note The Z180™ Interfaced with the SCC at MHZ 7-3 7 Table 1. Z8018010 Timing Parameters for Opcode Fetch Cycle (Worst Case: Z180 10 MHz)

Application Note The Z180™ Interfaced with the SCC at MHZ 7-4 EPROM INTERFACE During an Opcode fetch cycle, data sampling of the bus ison the rising

Application Note The Z180™ Interfaced with the SCC at MHZ 7-5 7 inserting wait states. With this scheme, you can get thehighest performance with mode

Application Note The Z180™ Interfaced with the SCC at MHZ 7-6 (Continued) Figure 4a. Memory Interface LogicG/G2A/G2BCBAA9A18A17A16A15/Y9/Y6/Y5/Y4

Application Note The Z180™ Interfaced with the SCC at MHZ 7-7 7 (Extends Opcode Fetch Cycle Only; Not Working in ZMode of Operation) Figure 5. Physi

Application Note The Z180™ Interfaced with the SCC at MHZ 8 Z180 TO I/O INTERFACE The Z180 I/O read/write cycle is similar to the Z80 CPU ifyou clear

Application Note The Z180™ Interfaced with the SCC at MHZ 7 7 .If you are familiar with the Z80 CPU design, the sameinterfacing logic applies to the

Application Note The Z180™ Interfaced with the SCC at MHZ 0 (Continued) When expanding this board to enable other peripherals,the decoded address

Application NoteThe Z180™ Interfaced with the SCC at MHZ7Write Cycle TimingFigure 11 illustrates the SCC Write cycle timing. Allregister addresses and

Application NoteThe Z180™ Interfaced with the SCC at MHZ (Continued)SCC Interrupt OperationUnderstanding SCC interrupt operations requires a basickno

ISCCUser ManualUM011002-0808132.2.3 Data Transfers All data transfers to and from the ISCC are done in bytes even though the data may at spe-cial tim

Application NoteThe Z180™ Interfaced with the SCC at MHZ7The SCC uses /INTACK (Interrupt Acknowledge) forrecognition of an interrupt acknowledge cycle

Application NoteThe Z180™ Interfaced with the SCC at MHZ7-14INPUT/OUTPUT CYCLESAlthough the SCC is a universal design, certain timingparameters differ

Application NoteThe Z180™ Interfaced with the SCC at MHZ7-157I/O Read CycleThese tables show that a delay of the falling edge of /RDsatisfies the SCC

Application NoteThe Z180™ Interfaced with the SCC at MHZ7-16 (Continued)If you are running your system slower than 8 MHz, removethe HCT74, D-Flip/Flo

Application NoteThe Z180™ Interfaced with the SCC at MHZ7-177During an Interrupt Acknowledge cycle, the SCC requiresboth /INTACK and /RD to be active

Application NoteThe Z180™ Interfaced with the SCC at MHZ7-18 (Continued)Figure 14. Z180 to SCC Interface Logic (Example)T1 T2 Tw T316100 ns112870 ns

Application NoteThe Z180™ Interfaced with the SCC at MHZ7The primary chip in this logic is the Shift register (HCT164),which generates /INTACK, /SCCRD

Application NoteThe Z180™ Interfaced with the SCC at MHZ (Continued)Figure 16a. ELPD Circuit ImplementationPage 191 of 316UM011002-0808

Application NoteThe Z180™ Interfaced with the SCC at MHZ7Figure 16b. ELPD Circuit ImplementationPage 192 of 316UM011002-0808

Application NoteThe Z180™ Interfaced with the SCC at MHZ (Continued)System CheckoutAfter completion of the board (PC board or wire wrappedboard, etc.

ISCCUser ManualUM011002-0808iiDO NOT USE IN LIFE SUPPORTLIFE SUPPORT POLICYZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN

ISCCUser ManualUM011002-080814In the DMA Read with Byte Swap enabled: In this table DMA read refers to a DMA controlled transfer from memory to the IS

Application NoteThe Z180™ Interfaced with the SCC at MHZ7-237Table 12. SCC Test Program – Interrupt for 180/SCC Application Board (Under Mode2 Interru

Application NoteThe Z180™ Interfaced with the SCC at MHZ (Continued);external/status interrupt service routineext_stat: ld a,10hout (scc_cont),a ;res

Application NoteThe Z180™ Interfaced with the SCC at MHZ7Table 13 shows a “macro” to enable the Z180 to use theZ80 Assembler, as well as register defi

Application NoteThe Z180™ Interfaced with the SCC at MHZ7-26 (Continued)bcr1l: equ 2eh ; DMA Byte Count Reg Ch1-lowbcr1h: equ 2fh ; DMA Byte Count Re

Application NoteThe Z180™ Interfaced with the SCC at MHZ7-277db 10000011Bendmotimr macrodb 11101101Bdb 10010011Bendmotdm macrodb 11101101Bdb 10001011B

Application NoteThe Z180™ Interfaced with the SCC at MHZ7-28 (Continued)Table 14 lists a program example for the Z180/SCC DMA transfer test.Table 14.

Application NoteThe Z180™ Interfaced with the SCC at MHZ7call initdmald b,0 ;init statusld a,00h ;load 1st data to be sentout (scc_data),ald a,1100110

Application NoteThe Z180™ Interfaced with the SCC at MHZ7-30 (Continued)initscc: ld hl,scctab ; initialize sccinit0: ld a,(hl)cp 0ffhret zout (scc_co

Application NoteThe Z180™ Interfaced with the SCC at MHZ7-317db 01h ;select WR1db 01100000b ;REQ on Rxdb 02h ;select WR2db 00h ;00h as vector basedb 0

Application NoteThe Z180™ Interfaced with the SCC at MHZ7-32 (Continued)db 01h ;select WR1db 11100000b ;enable DMAdb 0fh ;select WR15db 00000000b ;do

ISCCUser ManualUM011002-080815the contents of the register, the CPU either reads data, writes data, or satisfies an error con-dition. Two bits in the

Application NoteThe Z180™ Interfaced with the SCC at MHZ7-237First, this program (Table 14) initializes the SCC by:Async, X1 mode, 8-bit 1 stop, Non-p

9-1 8 A PPLICATION N OTE T HE Z ILOG D ATACOM F AMILY WITH THE 80186 CPU 8 ilog’s datacom family evaluation board features the 80186 along w

Application Note The Zilog Datacom Family with the 80186 CPU 9-2 GENERAL DESCRIPTION Processor The 80186 may be operated at rates up to 16 MHz. To

Application Note The Zilog Datacom Family with the 80186 CPU 9-3 8 Push buttons are provided for Reset and Non-MaskableInterrupt (NMI). A means to ge

Application Note The Zilog Datacom Family with the 80186 CPU 9-4 RAM Six 32-pin sockets are provided; they should be populatedin pairs, starting with

Application Note The Zilog Datacom Family with the 80186 CPU 9-5 8 The three LSBs of the above MMCS values are 111 so thatthe longest possible Reset

Application Note The Zilog Datacom Family with the 80186 CPU 9-6 (E)SCC Socket U2 can be configured for either an ESCC or SCC,and for versions thereo

Application Note The Zilog Datacom Family with the 80186 CPU 9-7 8 For a multiplexed part (80 x 30), the Select Shift Leftcommand (D1-0=11) should be

Application Note The Zilog Datacom Family with the 80186 CPU 9-8 The fact that the ISCC’s internal logic sees activity on its/AS pin, which is inve

Application Note The Zilog Datacom Family with the 80186 CPU 9-9 8 While the ESCC and ISCC can drive their Baud RateGenerators from their PCLK inputs

ISCCUser ManualUM011002-080816enabled, the CPU is interrupted when the transmit buffer becomes empty. This implies that data has shifted from the tran

Application NoteThe Zilog Datacom Family with the 80186 CPU9-10 IUSC (Continued)While the ESCC and ISCC can drive their Baud RateGenerators from their

Application NoteThe Zilog Datacom Family with the 80186 CPU9-118The pin-out of the J5-J10 connectors is fairly consistent,but of necessity not identic

Application NoteThe Zilog Datacom Family with the 80186 CPU9-12SERIAL INTERFACING (Continued)Comparison of the two preceding charts leads to severalco

Application NoteThe Zilog Datacom Family with the 80186 CPU9-138Sensing which Serial Controller Channel is connected to the ConsoleIn order to use the

Application NoteThe Zilog Datacom Family with the 80186 CPU9-14SERIAL INTERFACING (Continued)With jumpers installed to make DCD and CTS unbalanced,J4

Application NoteThe Zilog Datacom Family with the 80186 CPU9-158JUMPER SUMMARYTable 12 includes only those connector blocks intended tobe populated by

Application NoteThe Zilog Datacom Family with the 80186 CPU9-16DMA/EPLD LOGICFigure 1. Control EPLD for 186 BoardPage 220 of 316UM011002-0808

Application NoteThe Zilog Datacom Family with the 80186 CPU9-178Figure 2. SCC EPLD for 186 BoardPage 221 of 316UM011002-0808

Application NoteThe Zilog Datacom Family with the 80186 CPU9-18 DMA/EPLD LOGIC (Continued)Figure 3. DMA EPLD for 186 BoardPage 222 of 316UM011002-0808

Application NoteThe Zilog Datacom Family with the 80186 CPU9-198Figure 4. NMI Field for 186 BoardPage 223 of 316UM011002-0808

ISCCUser ManualUM011002-080817fer or until the terminal count is reached, or /BUSACK is deactivated. The four DMA channels operate independently when

Application NoteThe Zilog Datacom Family with the 80186 CPU9-20Figure 5. Schematic of the Evaluation BoardPage 224 of 316UM011002-0808

10-1 9 A PPLICATION N OTE SCC IN B INARY S YNCHRONOUS C OMMUNICATIONS 9 INTRODUCTION Zilog’s Z8030 Z-SCC Serial Communications Controller isone

Application Note SCC in Binary Synchronous Communications 10-2 SYNCHRONOUS MODES Three variations of character-oriented synchronouscommunications are

Application Note SCC in Binary Synchronous Communications 10-3 9 Figure 2. Block Diagram of Z8000 DMAddress/Data BufferWire Wrap AreaResetSwitchNMIS

Application Note SCC in Binary Synchronous Communications 10-4 SYSTEM INTERFACE (Continued) Figure 4. Z8002 with SCC4B3B2B1BGBA4A3A2A1A/GAB89101165

Application Note SCC in Binary Synchronous Communications 10-5 9 When the Z8002 CPU uses the lower half of theAddress/Data bus (AD0-AD7 the least sig

Application Note SCC in Binary Synchronous Communications 10-6 INITIALIZATION (Continued) The Z8002 CPU must be operated in System mode inorder to

Application Note SCC in Binary Synchronous Communications 10-7 9 TRANSMIT OPERATION To transmit a block of data, the main program calls up thetransmi

Application Note SCC in Binary Synchronous Communications 10-8 APPENDIX SOFTWARE ROUTINES plzasm 1.3LOC OBJ CODE STMT SOURCE STATEMENT 1 BISYNC MO

Application Note SCC in Binary Synchronous Communications 10-9 9 INITIALIZATION ROUTINE FOR Z-SCC 0034 GLOBALENTRYINIT PROCEDURE 0634 2100 LD R0, #15

ISCCUser ManualUM011002-080818In Shift Right Mode, bits 0-1 in WR0A controls which bits will be decoded to form the register address. It is placed in

Application Note SCC in Binary Synchronous Communications 10-10 RECEIVE ROUTINE RECEIVE A BLOCK OF MESSAGETHE LAST CHARACTER SHOULD BE EOT (%04) 006C

Application Note SCC in Binary Synchronous Communications 10-11 9 TRANSMIT ROUTINE SEND A BLOCK OF DATA CHARACTERSTHE BLOCK STARTS AT LOCATION TBUP O

Application Note SCC in Binary Synchronous Communications 10-12 RECEIVE INT. SERVICE ROUTINE 00F4GLOBALENTRY REC PROCEDURE 00F4 93F0 PUSH @RI5, R000F

Application Note SCC in Binary Synchronous Communications 10-13 9 SPECIAL CONDITION INTERRUPT SERVICE ROUTINE o errorsAssembly complete 011EGLOBALENT

11-1 1 A PPLICATION N OTE S ERIAL C OMMUNICATION C ONTROLLER (SCC ™ ): SDLC M ODE OF O PERATION 10 nderstanding the transactions which occur w

Application Note Serial Communication Controller (SCC ™ ): SDLC Mode of Operation 11-2 SDLC TRANSMIT Figure 1 shows the time chart for the transmitti

Application Note Serial Communication Controller (SCC ™ ): SDLC Mode of Operation 11-3 1 Notes on Figure 1:1. The SCC has two possible idle states, M

Application Note Serial Communication Controller (SCC ™ ): SDLC Mode of Operation 11-4 SDLC RECEIVE There are several different ways to receive a SDL

Application Note Serial Communication Controller (SCC ™ ): SDLC Mode of Operation 11-5 1 Figure 2. Typical SDLC Receive Sequence with Receive Interru

Application Note Serial Communication Controller (SCC ™ ): SDLC Mode of Operation 11-6 RECEIVE INTERRUPTS ON FIRST CHARACTER OR SPECIAL CONDITIONS Th

ISCCUser ManualUM011002-0808192.4.2 SCC Cell Register Access, Non-Multiplexed Bus The registers in the SCC cell in the non-multiplexed bus mode are

Application Note Serial Communication Controller (SCC ™ ): SDLC Mode of Operation 11-7 1 Notes on Figure 3: 1. The receiver is usually in hunt mode w

Application Note Serial Communication Controller (SCC ™ ): SDLC Mode of Operation 11-8 RECEIVE INTERRUPTS ON SPECIAL CONDITIONS ONLY The sequence of

Application Note Serial Communication Controller (SCC ™ ): SDLC Mode of Operation 11-9 1 Figure 4. Receiving “Back to Back” frame with Receive Interr

Application Note Serial Communication Controller (SCC ™ ): SDLC Mode of Operation 11-10 THE SDLC LOOP MODE The SDLC Loop mode is one of the protocol

Application Note Serial Communication Controller (SCC ™ ): SDLC Mode of Operation 11-11 1 Figure 6. SDLC Loop ModeTxD (Master), RxD (Slave)TxD (Slave

Application Note Serial Communication Controller (SCC ™ ): SDLC Mode of Operation 11-12 THE SDLC LOOP MODE (Continued) Notes on Figure 6: 1. The ma

12-1 1 A PPLICATION N OTE U SING SCC WITH Z8000 IN SDLC P ROTOCOL 11 INTRODUCTION This application note describes the use of the Z8030 SerialCo

Application Note Using SCC with Z8000 in SDLC Protocol 12-2 SDLC PROTOCOL Data communications today require a communicationsprotocol that can transfe

Application Note Using SCC with Z8000 in SDLC Protocol 12-3 1 The SDLC protocol differs from other synchronousprotocols with respect to frame timing.

Application Note Using SCC with Z8000 in SDLC Protocol 12-4 SYSTEM INTERFACE (Continued) Two Z8000 Development Modules containing SCCs areconnected

ISCCUser ManualUM011002-080820the pointer bits must be set by writing to WR0 bits 2, 1, and 0 and, if required, using the Point High command to extend

Application Note Using SCC with Z8000 in SDLC Protocol 12-5 1 Figure 5. Z8002 With SCCPage 254 of 316UM011002-0808

Application Note Using SCC with Z8000 in SDLC Protocol 12-6 INITIALIZATION The SCC can be initialized for use in different modes bysetting various bi

Application Note Using SCC with Z8000 in SDLC Protocol 12-7 1 TRANSMIT OPERATION To transmit a block of data, the main program calls up thetransmit d

Application Note Using SCC with Z8000 in SDLC Protocol 12-8 RECEIVE OPERATION (Continued) If receive overrun error is made, a special conditioninte

Application Note Using SCC with Z8000 in SDLC Protocol 12-9 1Page 258 of 316UM011002-0808

Application Note Using SCC with Z8000 in SDLC Protocol 12-10 SOFTWARE (Continued)Page 259 of 316UM011002-0808

Application Note Using SCC with Z8000 in SDLC Protocol 12-11 1Page 260 of 316UM011002-0808

Application Note Using SCC with Z8000 in SDLC Protocol 12-12 RECEIVE OPERATION (Continued)Page 261 of 316UM011002-0808

13-1 1 A PPLICATION N OTE B OOST Y OUR S YSTEM P ERFORMANCE U SING T HE Z ILOG ESCC ™ 12 for greater testability, larger interface flexibilit

Application Note Boost Your System Performance Using The Zilog ESCC ™ 13-2 ESCC/SCC DIFFERENCES The differences between the ESCC and SCC are shownbel

ISCCUser ManualUM011002-080821Table 2–4. SCC Cell Register Address Map Using Pointer (Non-multiplexed Bus Mode) Using Null CommandA1/A//BAddressD2 D1

Application Note Boost Your System Performance Using The Zilog ESCC ™ 13-3 1 Figure 2. Generic SCC/ESCC DriversSCCZ85C30ESCCZ85230Z85C30Initializatio

Application Note Boost Your System Performance Using The Zilog ESCC ™ 13-4 ESCC SYSTEM BENEFITS The Software Overhead sets the System PerformanceLimi

Application Note Boost Your System Performance Using The Zilog ESCC ™ 13-5 1 TRANSMIT FIFO INTERRUPT In the ESCC, transmit interrupt frequencies are

Application Note Boost Your System Performance Using The Zilog ESCC ™ 13-6 RECEIVE FIFO INTERRUPT In the ESCC, receive interrupt frequencies are redu

Application Note Boost Your System Performance Using The Zilog ESCC ™ 13-7 1 AUTOMATIC /RTS DEASSERTION Several SDLC enhancements are provided in the

Application Note Boost Your System Performance Using The Zilog ESCC ™ 13-8 AUTOMATIC OPENING FLAG TRANSMISSION When Auto Tx Flag (WR7', D0) is e

Application Note Boost Your System Performance Using The Zilog ESCC ™ 13-9 1 SDLC Frame Status FIFO enhancement is enabled bysetting WR15 D2. If it i

Application Note Boost Your System Performance Using The Zilog ESCC ™ 13-10 AUTOMATIC OPENING FLAG TRANSMISSION (Continued) Figure 10. SDLC Status

Application Note Boost Your System Performance Using The Zilog ESCC ™ 13-11 1 DMA Request on Transmit Deactivation Timing /DTR//REQ. Timing implement

Application Note Boost Your System Performance Using The Zilog ESCC ™ 13-12 AUTOMATIC OPENING FLAG TRANSMISSION (Continued) Figure 13. Transmission

ISCCUser ManualUM011002-0808222.4.3 SCC Cell Register ResetTable 2-5 lists the contents of the SCC cell registers after a hardware reset and after a

Application Note Boost Your System Performance Using The Zilog ESCC ™ 13-13 1 MODIFIED WRITE TIMING In the SCC write cycle, the SCC assumes the data

14-1 1 A PPLICATION N OTE T ECHNICAL C ONSIDERATIONS W HEN I MPLEMENTING L OCAL T ALK L INK A CCESS P ROTOCOL 13 he LLAP Protocol is an impo

Application Note Technical Considerations When Implementing LocalTalk Link Access Protocol 14-2 GENERAL DESCRIPTION (Continued) leaves room for pos

Application Note Technical Considerations When Implementing LocalTalk Link Access Protocol 14-3 1 Dynamic Node ID LLAP requires the use of an 8-bit n

Application Note Technical Considerations When Implementing LocalTalk Link Access Protocol 14-4 HARDWARE CONFIGURATION As shown in Figure 2, the hard

Application Note Technical Considerations When Implementing LocalTalk Link Access Protocol 14-5 1 Listing 1 (Reference Appendix A for Listings 1 thro

Application Note Technical Considerations When Implementing LocalTalk Link Access Protocol 14-6 TRANSMITTING A LLAP FRAME Listing 2 shows the assembl

Application Note Technical Considerations When Implementing LocalTalk Link Access Protocol 14-7 1 The second routine decrements the receiver bufferad

Application Note Technical Considerations When Implementing LocalTalk Link Access Protocol 14-8 APPENDIX AListing 1- Asembler Code for SCC Initializa

Application Note Technical Considerations When Implementing LocalTalk Link Access Protocol 14-9 1 00000212 0a 532 db 0ah ;WR1000000213 e0 533 db 0e

ISCCUser ManualUM011002-080823There are two address decoding modes: shift left and shift right. In shift left mode, the register address is decoded f

Application Note Technical Considerations When Implementing LocalTalk Link Access Protocol 14-10 LISTING 2 600 ;*************************************

14-11 1 0000027c d3e8 660 out (scc_cont),a0000027e 3e6b 661 ld a,01101011b ;sdlc crc,662 ;txcrc enable,663 ;reset rts00000280 d3e8 664 out (scc_co

13-142 000002bb 10f0 722 djnz txq2 ;loop until all723 ;bytes have been 724 ;transmitted.725 726 000002bd 3e28 727 ld a,028h ;reset tx int pending0

Application Note Technical Considerations When Implementing LocalTalk Link Access Protocol 14-5 1 784 ;subroutine to time out bit time 4.3 usec per

Application Note Technical Considerations When Implementing LocalTalk Link Access Protocol 14-6 LISTING 3 1131 ;******************************1132 ;r

Application Note Technical Considerations When Implementing LocalTalk Link Access Protocol 14-7 1 00000488 1186 ok:00000488 21Wwww 1187 ld hl,recerrfl

Application Note Technical Considerations When Implementing LocalTalk Link Access Protocol 14-8 LISTING 4 1306 1307 ;********************************

Application Note Technical Considerations When Implementing LocalTalk Link Access Protocol 14-9 1 00001000 1365 org 1000h00001000 1366 rx_buff: .blo

Application Note Technical Considerations When Implementing LocalTalk Link Access Protocol 14-10 APPENDIX B 12 to 18 1’s at the end of an LLAP frameP

Application Note Technical Considerations When Implementing LocalTalk Link Access Protocol 14-11 1 CSMA/CA before an LLAP framePage 293 of 316UM01100

ISCCUser ManualUM011002-0808 Revision HistoryiiiRevision HistoryEach instance in Revision History reflects a change to this document from its previous

ISCCUser ManualUM011002-080824Table 2–6. DMA Address MapAddress* Name Description xxxxx BCR Bus Configuration Register 00000 CCAR Channel Command/

Application Note Technical Considerations When Implementing LocalTalk Link Access Protocol 14-12 An LLAP FramePage 294 of 316UM011002-0808

15-1 1 A PPLICATION N OTE O N -C HIP O SCILLATOR D ESIGN 14 esign and build reliable, cost-effective, on-chip oscillator circuits that are trouble

Application Note On-Chip Oscillator Design 15-2 OSCILLATOR THEORY OF OPERATION (Continued) Pierce Oscillator (Feedback Type) The basic circuit an

Application Note On-Chip Oscillator Design 15-3 1 However, there are several ranges of frequencies wherethe reactance is positive; these are the fund

Application Note On-Chip Oscillator Design 15-4 OSCILLATOR THEORY OF OPERATION (Continued) Series vs. Parallel Resonance. There is very littledif

Application Note On-Chip Oscillator Design 15-5 1 Load Capacitors The effects/purposes of the load caps are:Cap C2 combined with the amp output resis

Application Note On-Chip Oscillator Design 15-6 PRACTICE: CIRCUIT ELEMENT AND LAY OUT CONSIDERATIONS The discussion now applies prior theory to the p

Application Note On-Chip Oscillator Design 15-7 1 Load Capacitors In the selection of load caps it is understood that parasiticsare always included.

Application NoteOn-Chip Oscillator Design15-8 PRACTICE: CIRCUIT ELEMENT AND LAY OUT CONSIDERATIONS (Continued)Output Level. The signal at the amplifie

On-Chip Oscillator Design15-91SUMMARYUnderstanding the Theory of Operation of oscillators,combined with practical applications, should givedesigners e

ISCCUser ManualUM011002-080825Note: *Address in this Table is AD5-AD1 in the Multiplexed Bus with the Shift Left mode selected, AD4-AD0 in the Multi

14-160REFERENCES MATERIALS AND ACKNOWLEDGEMENTSIntel Corp., Application Note AP-155, “Oscillators for MicroControllers”, order #230659-001, by Tom Wil

16-1 A PPLICATION N OTE I NTERFACING THE ISCC™ TO THE 68000 AND 8086 INTRODUCTION The ISCC™ uses its flexible bus to interface with a varie

Application Note Interfacing the ISCC™ to the 68000 and 8086 16-2 ISCC BUS INTERFACE UNIT (BIU) (Continued) the ISCC is a slave peripheral; they be

Application Note Interfacing the ISCC™ to the 68000 and 8086 16-3 BUS DATA TRANSFERS All data transfers to and from the ISCC™ are done in bytesregard

Application Note Interfacing the ISCC™ to the 68000 and 8086 16-4 BUS DATA TRANSFERS (Continued) determines which byte of the bus data is accepted.

Application Note Interfacing the ISCC™ to the 68000 and 8086 16-5 CONFIGURING THE BUS The bus configuration programming is done in twoseparate steps

Application Note Interfacing the ISCC™ to the 68000 and 8086 16-6 APPLICATIONS EXAMPLES The following application examples explain and illustratethe

Application Note Interfacing the ISCC™ to the 68000 and 8086 16-7 Figure 3. ISCC Interface to a 68000 Microprocessor/UDS/RESET/UDS/LDS/DTACKD15-0A23-

Application Note Interfacing the ISCC™ to the 68000 and 8086 16-8 APPLICATIONS EXAMPLES (Continued) Figure 4. ISCC Interface to an Intel 8086 Micro

Application Note Interfacing the ISCC™ to the 68000 and 8086 16-9When the ISCC becomes a bus master during DMAoperations, RD and WR of the 8086 are t

ISCCUser ManualUM011002-080826Chapter 3 ISCC™ DMA and Ancillary Support Circuitry3.1 INTRODUCTION The most important feature of the ISCC other than

Application Note Interfacing the ISCC™ to the 68000 and 8086 16-10To start, the BCR write (first write to the ISCC afterRESET) is done with A7 = 1 (A

18-1 Z ILOG ISCC ™ C ONTROLLER Q UESTIONS AND A NSWERS ISCC QUESTIONS AND ANSWERS Q. Is the interrupt vector present on both the lower 8 b

Z16C35 ISCC™ User’s Manual Zilog ISCC ™ Controller 18-2 ISCC QUESTIONS AND ANSWERS (Continued) Q. What’s the recovery time required for the ISCC?

ISCCUser ManualUM011002-080827An Interrupt Pending only modifies the interrupt vector if the corresponding Interrupt Enable bit is set. Note that soft

ISCCUser ManualUM011002-0808283.2.2 Transmitter DMA Operation With the DMA enabled, the status of an empty transmitter FIFO triggers the DMA to reque

ISCCUser ManualUM011002-080829When the time-constant is to be changed, the generator should be stopped first by writing to an enable bit in WR14. Afte

ISCCUser ManualUM011002-080830Figure 3–5. Baud Rate Generator Start-UpThe formulas relating the baud rate to the time-constant and vice versa are show

ISCCUser ManualUM011002-080831Initializing the baud rate generator is done in three steps. First, the time-constant is deter-mined and loaded into WR1

ISCCUser ManualUM011002-080832 Figure 3–6. Data Encoding MethodsIn NRZ, encoding a “1” is represented by a HIGH level and a “0” is represented by a LO

ISCCUser ManualUM011002-080833Manchester encoding, which is not directly supported, always produces a transition at the center of the bit cell. If the

Z8 CPU CoreUser ManualUM011002-0808 Table of ContentsivTable of ContentsGeneral Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ISCCUser ManualUM011002-080834The first command selects the baud rate generator as the clock source. The other command selects /RTxC pin as the clock

ISCCUser ManualUM011002-080835the receiver samples the data in the middle of the bit cell. In NRZI mode, the DPLL does not require a transition in eve

ISCCUser ManualUM011002-080836If the transition occurs between count 0 and the middle of count 15, the output of the DPLL is sampling the data too lat

ISCCUser ManualUM011002-080837counter dependent upon which region the transition on the receive data input occurred. This is shown in Figure 3-7.Figur

ISCCUser ManualUM011002-080838or programmed to enter the Search mode. Upon missing this one edge, the DPLL takes no other action and does not modify i

ISCCUser ManualUM011002-080839Figure 3–11. Encoding Manchester DataTransmit Clock12345NRZabManchesterNRZTransmit Clock12345Page 39 of 316

ISCCUser ManualUM011002-0808403.6 CLOCK SELECTION The ISCC can select several clock sources for internal and external use. Write Register 11 is the C

ISCCUser ManualUM011002-080841Figure 3–12. Clock MultiplexerSelection of the clocking options may be done anywhere in the initialization sequence, but

ISCCUser ManualUM011002-080842Figure 3–13. Async Transmission, 16x Clock Mode Using External CrystalFigure 3–14. Async Transmission, 1x Clock Rate, NR

ISCCUser ManualUM011002-080843Figure 3–15. Asynchronous Transmission, 1x Clock Rate, FM Data EncodingFig 3-10 shows the clock set up for asynchronous

Z8 CPU CoreUser ManualUM011002-0808 Table of ContentsvGeneral Description of the Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ISCCUser ManualUM011002-080844•Set FM mode WR14. •Set FM mode WR10. 3.7 CRYSTAL OSCILLATORS For a given channel, if bit D7 of WR11 is set to 1, the c

ISCCUser ManualUM011002-080845Chapter 4 Data Communication Modes4.1 INTRODUCTION The ISCC™ provides two independent full-duplex channels programmabl

ISCCUser ManualUM011002-080846 Figure 4–16. Transmitter Block DiagramIf asynchronous data is processed, WR6 and WR7 are not used and the Transmit Shif

ISCCUser ManualUM011002-0808474.1.2 General Description of the Receiver The receiver has a three deep, 8-bit Data FIFO (paired with a three deep Erro

ISCCUser ManualUM011002-080848The incoming data then passes through the Sync register and is compared to a sync charac-ter stored in WR6 or WR7 (depen

ISCCUser ManualUM011002-0808494.2 ASYNCHRONOUS MODE In asynchronous communications data is transferred in the format shown in Figure 4-3. Figure 4–1

ISCCUser ManualUM011002-080850WR7 and all of WR10 except D6 and D5. Bits that are ignored may be programmed with “1” or “0” or not at all. See Table 4

ISCCUser ManualUM011002-080851For five or less bits per character selection in WR5, the following encoding is used in the data sent to the transmitter

ISCCUser ManualUM011002-080852mand is issued, until the first transmit clock edge after this bit is reset. The transmit clock edges referred to here a

ISCCUser ManualUM011002-080853The additional parity bit per character is transferred to the receive data FIFO along with the data if the data plus par

Z8 CPU CoreUser ManualUM011002-0808 Table of Contentsvi Read Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ISCCUser ManualUM011002-080854the data FIFO. The three error conditions that the receiver checks for in asynchronous mode are: 1. Framing errors - whe

ISCCUser ManualUM011002-080855the character boundaries (i.e., achieving synchronization) is with a logic signal that goes active just as the first cha

ISCCUser ManualUM011002-080856modem that encodes or decodes clock information in the modulation process. Refer to the Monosync message format as shown

ISCCUser ManualUM011002-080857In character-oriented modes, a special bit pattern is used to provide character synchroniza-tion. The ISCC offers severa

ISCCUser ManualUM011002-080858occur when the character moves from the buffer to the shift register. Once the buffer becomes empty, the Tx CRC Enable b

ISCCUser ManualUM011002-080859At this point, the other registers should be initialized as necessary. When all of this is com-pleted the transmitter ma

ISCCUser ManualUM011002-080860Figure 4–20. sync Character ProgrammingFor those applications requiring any other sync character length, the ISCC makes

ISCCUser ManualUM011002-080861 This is shown in Figure 4-6. The receiver leaves Hunt mode when /SYNC is driven Low. Figure 4–21. /SYNC as an InputIn a

ISCCUser ManualUM011002-080862The receiver in the ISCC searches for character synchronization only while it is in Hunt mode. In this mode the receiver

ISCCUser ManualUM011002-080863Figure 4–23. Changing Character LengthEither of two CRC polynomials may be used in synchronous modes, selected by bit D2

ISCCUser ManualUM011002-08081Chapter 1 General Description1.1 INTRODUCTION The Z16C35, ISCC is a CMOS superintegration device with a flexible Bus In

ISCCUser ManualUM011002-080864receive data FIFO. As previously mentioned, 8-bit sync characters stripped from the data stream are automatically exclud

ISCCUser ManualUM011002-0808655. At the end of eight-bit-times F is in the 8-bit delay and G is in the Receive Shift regis-ter. At this time G is tran

ISCCUser ManualUM011002-080866Table 4–16. Enabling and Disabling CRC on the FlyDirection of DataComing into SCCShiftRegisterDelayRegisterCRC NotesH G

ISCCUser ManualUM011002-080867Up to two modem control signals associated with the receiver are available in synchronous modes: DTR/REQ and DCD. The /D

ISCCUser ManualUM011002-0808684.3.3 Transmitter/Receiver Synchronization The ISCC contains a transmitter-to-receiver synchronization function that ma

ISCCUser ManualUM011002-080869enabled by setting bit D0 of WR3 to “1”. If the receiver is already enabled it may be placed in Hunt mode by setting bit

ISCCUser ManualUM011002-080870receiver then removes the “0” following a received succession of five “1s”. Inserted and removed “0s” are not included i

ISCCUser ManualUM011002-080871underrun occurs. The frame will be terminated normally, with CRC and a flag, if this bit is set to “0”, and the Tx Under

ISCCUser ManualUM011002-080872Only the CRC-CCITT polynomial may be used in SDLC mode. This is selected by setting bit D2 in WR5 to “0”. This bit contr

ISCCUser ManualUM011002-080873Underrun Latch can be read in RR0. The Tx Underrun Latch may be reset by the processor via WR0. For correct transmission

ISCCUser ManualUM011002-08082Figure 1–1. Block Diagram1.2 Features•Low Power CMOS Technology •Two General-Purpose SCC Channels, Four DMA Channels; an

ISCCUser ManualUM011002-0808744.4.2 SDLC Receive The receiver in the ISCC™ always searches the receive data stream for flag characters in SDLC mode.

ISCCUser ManualUM011002-080875 Figure 4–27. /SYNC as an OutputIf the Address Search Mode bit (D2) in WR3 is set to “0” the address recognition logic i

ISCCUser ManualUM011002-080876Figure 4–28. Changing Character LengthMost bit-oriented protocols allow an arbitrary number of bits between opening and

ISCCUser ManualUM011002-080877Table 4–20. Residue Codes As indicated in the table, these bits allow the processor todetermine those bits in the infor-

ISCCUser ManualUM011002-080878set value. If this bit is set to “1”, the generator and checker are preset to “1s”, if this bit is reset, the generator

ISCCUser ManualUM011002-080879“0” is received, either by itself or as the leading “0” of a flag. The receiver does not leave Hunt mode until a flag ha

ISCCUser ManualUM011002-080880The receiver searches for synchronization when it is in Hunt mode. In this mode the receiver is idle except that it is s

ISCCUser ManualUM011002-080881delay, and doesn’t be-gin transmitting until it receives the second EOP. There are also two additional status bits in RR

ISCCUser ManualUM011002-080882If SDLC loop is deselected, the ISCC is designed to exit from the loop gracefully. When SDLC Loop mode is deselected by

ISCCUser ManualUM011002-080883 Then the Loop Mode bit (D1) in WR10 should be set to “1”. When all of this is complete the transmitter may be enabled b

ISCCUser ManualUM011002-08083•Independent DMA Register Set •A Universal Bus Interface Unit Providing Simple Interface to Most CPUs Multiplexed or Non-

ISCCUser ManualUM011002-080884point the processor may either write the first character to the transmit buffer and wait for a transmit buffer empty con

ISCCUser ManualUM011002-080885If the data is written immediately after the Go Active On Poll bit has been set, the ISCC will only insert one flag afte

ISCCUser ManualUM011002-080886Chapter 5 Register Descriptions5.1 INTRODUCTION This section describes the function of the various bits in the registe

ISCCUser ManualUM011002-0808875.2.2 Read Registers, SCC Cell Four read registers indicate status information, two are for baud rate generation, and o

ISCCUser ManualUM011002-0808885.2.3 DMA Registers The DMA cell contains 16 read write registers for control of the DMA channels. The DMA possesses it

ISCCUser ManualUM011002-0808895.3 SCC CELL REGISTER OVERVIEW The SCC cell write register set in each channel includes ten control registers (among th

ISCCUser ManualUM011002-0808905.4.1 Write Register 0 (Command Register) WR0 is the command register and the CRC reset code register. WR0 takes on sli

ISCCUser ManualUM011002-080891Figure 5-2 shows the bit configuration for the multiplexed mode and includes (in Channel B only) the address decoding se

ISCCUser ManualUM011002-080892Bit combination 10 is the Reset Transmit CRC Generator Command This command initializes the CRC generator. It is usually

ISCCUser ManualUM011002-080893Bit combination 011 is the Send Abort Command This command is used in SDLC mode to transmit a sequence of eight to thirt