Zilog Z16C30 Uživatelský manuál stáhnout pdf (Strana 42)

2-16

Z16C30 USC

USER'S MANUAL

UM97USC0100

ZILOG

2.9.7 Register Read and Write Cycles (Continued)

ADnn

A//B, D//C

/CS

/SITACK

/PITACK, /RD,(/WR or /DS),

DMA Acknowledge signals

/AS

R//W

(Required with /DS, not with /WR.)

/DS or /WR

Wait Mode

/WAIT//RDY

Address Data

Acknowledge Mode

Figure 2-11. A Register Write Cycle with Multiplexed Addresses and Data

UM009402-0201

1 2 ... 37 38 39 40 41 42 43 44 45 46 47 ... 207 208

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Zilog Z16C30 Uživatelský manuál Strana 42