Zilog Z16C30 Uživatelský manuál stáhnout pdf (Strana 150)

7-22

Z16C30 USC

USER'S MANUAL

UM97USC0100

ZILOG

7.14 CHANNEL INTERRUPT OPTIONS

Figure 7-17 shows that the MSByte of the Interrupt Control

rupts from a USC channel. These bits are fully under

software control and can be read or written at any time.

The Master Interrupt Enable bit (MIE; ICR15) must be set

to 1 to allow the channel to request an interrupt on its /INT

pin.

7.13 INTERRUPT ENABLE BITS

Software can read, set, and clear the Interrupt Enable (IE)

bits for all six interrupt types in a USC channel, in the

LSByte of its Interrupt Control Register (ICR). Figure 7-17

shows the ICR. Software can read all six IE bits from ICR5-

0; ICR7-6 always read as 00. When software writes the

LSByte of the ICR, the IE Op field (ICR7-6) comprises a

command that the channel applies to any and all IE bits

selected by ones written to ICR5-0. The channel interprets

IE Op as follows:

IE Op Operation

0x No operation

10 Clear the IE bit(s) of the type(s) selected in

ICR5-0

11 Set the IE bit(s) of the type(s) selected in

ICR5-0

Whenever the Disable Lower Chain bit (DLC; ICR14) is 1,

the channel forces its IEO output low, so that devices

further down the daisy chain can’t request interrupts nor

respond to interrupt acknowledge cycles.

If the No Vector bit (NV; ICR13) is 1, the channel neither

provides a vector nor drives the /WAIT//RDY pin during an

interrupt acknowledge cycle in which the highest-priority

requesting type is in the channel. However, in such a case

the channel still sets the IUS bit of the highest-priority

requesting type.

14 13 12 11 10 9 8 7 6 5 4 3 2 1 015

IUSCmd

(WO)

IOP

IUS

IPCmd

(WO)

IUS

Misc

IUSC

IOP

Misc

Figure 7-16. The Daisy Chain Control Register (DCCR)

14 13 12 11 10 9 8 7 6 5 4 3 2 1 015

MIE

IECmd

(WO)

VIS

Rsrvd

IOP

Misc

DLC

Figure 7-17. The Interrupt Control Register (ICR)

UM009402-0201

1 2 ... 145 146 147 148 149 150 151 152 153 154 155 ... 207 208

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