Zilog Z80180 Uživatelský manuál stáhnout pdf (Strana 122)

Z8018x

Family MPU User Manual

UM005003-0703

107

Memory to I/O (Memory Mapped I/O) — Channel 0

For memory to/from I/O (and memory to/from memory mapped I/O) the

DREQ

0 input is used to time the DMA transfers. In addition, the TEND0

(Transfer End) output is used to indicate the last (byte count register

BCR0 =

00H) transfer.

The DREQ0

input can be programmed as level- or edge-sensitive.

When level-sense is programmed, the DMA operation begins when

DREQ

0 is sampled Low. If DREQ0 is sampled High, after the next DMA

byte transfer, control is relinquished to the Z8X180 CPU. As illustrated in

Figure 47, DREQ

0 is sampled at the rising edge of the clock cycle prior to

T3, (that is, either T2

or Tw).

Figure 47. CPU Operation and DMA Operation DREQ0 is Programmed

for Level-Sense

When edge-sense is programmed, DMA operation begins at the falling

edge of DREQ

0 If another falling edge is detected before the rising edge

of the clock prior to T3 during DMA write cycle (that is T2 or Tw), the

DMAC continues operating. If an edge is not detected, the CPU is given

control after the current byte DMA transfer completes. The CPU

continues operating until a DREQ

0 falling edge is detected before the

Tw T1 T2 T3Tw Tw TwT1 T1 T1T2 T2 T2T3 T3T3

DMA

CPU

DMA DMA

** **

** DREQ0

is sampled at

DREQ0

Phi

Write

Cycle

Machine

Cycle

Read

Cycle

Write

Cycle (I/O)

1 2 ... 117 118 119 120 121 122 123 124 125 126 127 ... 325 326

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