Zilog Z08470 Uživatelský manuál stáhnout pdf (Strana 267)

Z80 CPU Peripherals

User Manual

UM008101-0601 Serial Input/Output

247

3. ToforcetheZ80SIOtosendCRC,theCPUissuestheReset

Transmit Underrun/EOM Latch command (WR0) and satisfies the

interrupt with the Reset Transmit Interrupt Pending command. (This

command prevents the Z80 SIO from requesting more data.) Because

of the transmit underrun caused by this command, the Z80 SIO starts

sending CRC. The Z80 SIO also causes an External/Status interrupt

with the Transmit Underrun/EOM latch set.

4. The CPU satisfies this interrupt by loading pad characters to the transmit

buffer and issuing the Reset External/Status Interrupt command.

5. With this sequence, CRC is followed by a pad character instead of a

sync character. The Z80 SIO interrupts with a Transmit Buffer Empty

interrupt when CRC is completely sent and that the pad character is

loaded to the transmit shift register.

6. From this point on the CPU can send more pad characters or sync

characters.

Bisync CRC Generation

Setting the Transmit CRC enable bit (WR5, D0) initiates CRC accumula-

tion when the program sends the first data character to the Z80 SIO.

Although the Z80 SIO automatically transmits up to two sync characters

(18-bit sync), it is recommended to send a few more sync characters ahead

of the message (before enabling Transmit CRC) to ensure synchronization

at the receiving end.

The transmit CRC Enable bit can be changed at any time in the message to

include or exclude a particular data character from CRC accumulation. The

Transmit CRC Enable bit should be in the suitable state when the data char-

acter is loaded from the transmit data buffer to the transmit shift register. To

ensure this bit is in a suitable state, the Transmit CRC Enable bit must be

issued before sending the data character to the Z80 SIO.

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Zilog Z08470 Uživatelský manuál Strana 267