Zilog EZ80L92 Uživatelský manuál stáhnout pdf (Strana 81)

eZ80L92 Development Kit

User Manual

UM012913-0407 General Array Logic Equations

wire nCS_EX,

nmemen1,

nmemen2,

nmemen3,

nmemen4;

//wire MOD_DIS =

((nmemen1==0)|(nmemen2==0)|(nmemen3==0)|(nmemen4==0));//if any

//of the signals is Low,

//Flash on the Module will be

//disabled if nDIS_FL is High

wire nEXP_EN = ~((nCS0==0)&(A7==0)&(A6==1));//expansion module

//Flash enabled if this is 0

//wire nDIS_FL = (nFL_DIS) ? ~nEXP_EN : ~(nFL_DIS);

wire nDIS_FL = nFL_DIS & nEXP_EN; //if either of them is 0 Flash is

//disabled

assign nCS_EX = (nEX_FL_DIS) ? nEXP_EN : ~(nEX_FL_DIS);

assign nL_RD =

~((nmemen1==0)|(nmemen2==0)|(nmemen3==0)|(nmemen4==0)|(nEM_EN==0

)|(nCS_EX==0));

assign nmemen4 = ~((nCS2==0)&({A7,A6,A5,A4,A3}==5'h17));

assign nmemen3 = ~((nCS2==0)&({A7,A6,A5,A4,A3}==5'h16));

assign nmemen2 = ~((nCS2==0)&({A7,A6,A5,A4,A3}==5'h15));

assign nmemen1 = ~((nCS2==0)&({A7,A6,A5,A4,A3}==5'h14));

assign nEM_EN = ~((nCS2==0)&({A7,A6,A5,A4,A3,A2,A1,A0}==8'h80));

endmodule

U15 Address Decoder

`define anode 8'h00

`define cathode 8'h01

`define latch 8'h02

// FOR eZ80

Development Platform Rev B

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